1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 #include <asm/arch/stm32.h>
11 #include <asm/arch/sys_proto.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
21 #include <env_internal.h>
23 #include <generic-phy.h>
26 #include <i2c_eeprom.h>
35 #include <power/regulator.h>
36 #include <remoteproc.h>
40 #include <usb/dwc2_udc.h>
43 /* SYSCFG registers */
44 #define SYSCFG_BOOTR 0x00
45 #define SYSCFG_PMCSETR 0x04
46 #define SYSCFG_IOCTRLSETR 0x18
47 #define SYSCFG_ICNR 0x1C
48 #define SYSCFG_CMPCR 0x20
49 #define SYSCFG_CMPENSETR 0x24
50 #define SYSCFG_PMCCLRR 0x44
52 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
53 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
55 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
56 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
57 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
58 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
59 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
61 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
62 #define SYSCFG_CMPCR_READY BIT(8)
64 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
66 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
67 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
69 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
71 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
72 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
73 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
74 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
77 * Get a global data pointer
79 DECLARE_GLOBAL_DATA_PTR;
81 int setup_mac_address(void)
83 unsigned char enetaddr[6];
87 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
88 if (ret) /* ethaddr is already set */
91 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
93 printf("%s: No eeprom0 path offset\n", __func__);
97 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
99 printf("Cannot find EEPROM!\n");
103 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
105 printf("Error reading configuration EEPROM!\n");
109 if (is_valid_ethaddr(enetaddr))
110 eth_env_set_enetaddr("ethaddr", enetaddr);
118 const char *fdt_compat;
121 if (IS_ENABLED(CONFIG_TFABOOT))
126 printf("Board: stm32mp1 in %s mode", mode);
127 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
129 if (fdt_compat && fdt_compat_len)
130 printf(" (%s)", fdt_compat);
136 #ifdef CONFIG_BOARD_EARLY_INIT_F
137 static u8 brdcode __section("data");
138 static u8 ddr3code __section("data");
139 static u8 somcode __section("data");
141 static void board_get_coding_straps(void)
143 struct gpio_desc gpio[4];
147 node = ofnode_path("/config");
148 if (!ofnode_valid(node)) {
149 printf("%s: no /config node?\n", __func__);
157 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
158 gpio, ARRAY_SIZE(gpio),
160 for (i = 0; i < ret; i++)
161 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
163 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
164 gpio, ARRAY_SIZE(gpio),
166 for (i = 0; i < ret; i++)
167 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
169 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
170 gpio, ARRAY_SIZE(gpio),
172 for (i = 0; i < ret; i++)
173 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
175 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
176 somcode, ddr3code, brdcode);
179 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
183 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
187 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
191 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
197 int board_early_init_f(void)
199 board_get_coding_straps();
204 #ifdef CONFIG_SPL_LOAD_FIT
205 int board_fit_config_name_match(const char *name)
209 snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
211 if (!strcmp(name, test))
219 static void board_key_check(void)
221 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
223 struct gpio_desc gpio;
224 enum forced_boot_mode boot_mode = BOOT_NORMAL;
226 node = ofnode_path("/config");
227 if (!ofnode_valid(node)) {
228 debug("%s: no /config node?\n", __func__);
231 #ifdef CONFIG_FASTBOOT
232 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
233 &gpio, GPIOD_IS_IN)) {
234 debug("%s: could not find a /config/st,fastboot-gpios\n",
237 if (dm_gpio_get_value(&gpio)) {
238 puts("Fastboot key pressed, ");
239 boot_mode = BOOT_FASTBOOT;
242 dm_gpio_free(NULL, &gpio);
245 #ifdef CONFIG_CMD_STM32PROG
246 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
247 &gpio, GPIOD_IS_IN)) {
248 debug("%s: could not find a /config/st,stm32prog-gpios\n",
251 if (dm_gpio_get_value(&gpio)) {
252 puts("STM32Programmer key pressed, ");
253 boot_mode = BOOT_STM32PROG;
255 dm_gpio_free(NULL, &gpio);
259 if (boot_mode != BOOT_NORMAL) {
260 puts("entering download mode...\n");
261 clrsetbits_le32(TAMP_BOOT_CONTEXT,
262 TAMP_BOOT_FORCED_MASK,
268 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
270 #include <usb/dwc2_udc.h>
271 int g_dnl_board_usb_cable_connected(void)
273 struct udevice *dwc2_udc_otg;
276 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
277 DM_GET_DRIVER(dwc2_udc_otg),
280 debug("dwc2_udc_otg init failed\n");
282 return dwc2_udc_B_session_valid(dwc2_udc_otg);
285 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
286 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
288 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
290 if (!strcmp(name, "usb_dnl_dfu"))
291 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
292 else if (!strcmp(name, "usb_dnl_fastboot"))
293 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
296 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
301 #endif /* CONFIG_USB_GADGET */
304 static int get_led(struct udevice **dev, char *led_string)
309 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
311 pr_debug("%s: could not find %s config string\n",
312 __func__, led_string);
315 ret = led_get_by_label(led_name, dev);
317 debug("%s: get=%d\n", __func__, ret);
324 static int setup_led(enum led_state_t cmd)
329 ret = get_led(&dev, "u-boot,boot-led");
333 ret = led_set_state(dev, cmd);
338 static void __maybe_unused led_error_blink(u32 nb_blink)
350 ret = get_led(&led, "u-boot,error-led");
352 /* make u-boot,error-led blinking */
353 /* if U32_MAX and 125ms interval, for 17.02 years */
354 for (i = 0; i < 2 * nb_blink; i++) {
355 led_set_state(led, LEDST_TOGGLE);
362 /* infinite: the boot process must be stopped */
363 if (nb_blink == U32_MAX)
367 static void sysconf_init(void)
369 #ifndef CONFIG_TFABOOT
371 #ifdef CONFIG_DM_REGULATOR
372 struct udevice *pwr_dev;
373 struct udevice *pwr_reg;
380 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
382 /* interconnect update : select master using the port 1 */
385 /* today information is hardcoded in U-Boot */
386 writel(BIT(9), syscfg + SYSCFG_ICNR);
388 /* disable Pull-Down for boot pin connected to VDD */
389 bootr = readl(syscfg + SYSCFG_BOOTR);
390 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
391 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
392 writel(bootr, syscfg + SYSCFG_BOOTR);
394 #ifdef CONFIG_DM_REGULATOR
395 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
396 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
397 * The customer will have to disable this for low frequencies
398 * or if AFMUX is selected but the function not used, typically for
399 * TRACE. Otherwise, impact on power consumption.
402 * enabling High Speed mode while VDD>2.7V
403 * with the OTP product_below_2v5 (OTP 18, BIT 13)
404 * erroneously set to 1 can damage the IC!
405 * => U-Boot set the register only if VDD < 2.7V (in DT)
406 * but this value need to be consistent with board design
408 ret = uclass_get_device_by_driver(UCLASS_PMIC,
409 DM_GET_DRIVER(stm32mp_pwr_pmic),
412 ret = uclass_get_device_by_driver(UCLASS_MISC,
413 DM_GET_DRIVER(stm32mp_bsec),
416 pr_err("Can't find stm32mp_bsec driver\n");
420 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
424 /* get VDD = vdd-supply */
425 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
428 /* check if VDD is Low Voltage */
430 if (regulator_get_value(pwr_reg) < 2700000) {
431 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
432 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
433 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
434 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
435 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
436 syscfg + SYSCFG_IOCTRLSETR);
439 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
442 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
445 debug("VDD unknown");
450 /* activate automatic I/O compensation
451 * warning: need to ensure CSI enabled and ready in clock driver
453 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
455 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
457 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
461 static void board_init_fmc2(void)
463 #define STM32_FMC2_BCR1 0x0
464 #define STM32_FMC2_BTR1 0x4
465 #define STM32_FMC2_BWTR1 0x104
466 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
467 #define STM32_FMC2_BCRx_FMCEN BIT(31)
468 #define STM32_FMC2_BCRx_WREN BIT(12)
469 #define STM32_FMC2_BCRx_RSVD BIT(7)
470 #define STM32_FMC2_BCRx_FACCEN BIT(6)
471 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
472 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
473 #define STM32_FMC2_BCRx_MUXEN BIT(1)
474 #define STM32_FMC2_BCRx_MBKEN BIT(0)
475 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
476 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
477 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
478 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
479 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
480 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
482 #define RCC_MP_AHB6RSTCLRR 0x218
483 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
484 #define RCC_MP_AHB6ENSETR 0x19c
485 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
487 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
488 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
489 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
490 STM32_FMC2_BCRx_MBKEN;
491 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
492 STM32_FMC2_BTRx_BUSTURN(2) |
493 STM32_FMC2_BTRx_DATAST(0x22) |
494 STM32_FMC2_BTRx_ADDHLD(2) |
495 STM32_FMC2_BTRx_ADDSET(2);
497 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
498 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
499 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
501 /* KS8851-16MLL -- Muxed mode */
502 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
503 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
504 /* AS7C34098 SRAM on X11 -- Muxed mode */
505 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
506 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
508 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
511 /* board dependent setup after realloc */
516 /* address of boot parameters */
517 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
519 /* probe all PINCTRL for hog */
520 for (uclass_first_device(UCLASS_PINCTRL, &dev);
522 uclass_next_device(&dev)) {
523 pr_debug("probe pincontrol = %s\n", dev->name);
528 #ifdef CONFIG_DM_REGULATOR
529 regulators_enable_boot_on(_DEBUG);
536 if (CONFIG_IS_ENABLED(LED))
542 int board_late_init(void)
545 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
546 const void *fdt_compat;
549 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
551 if (fdt_compat && fdt_compat_len) {
552 if (strncmp(fdt_compat, "st,", 3) != 0)
553 env_set("board_name", fdt_compat);
555 env_set("board_name", fdt_compat + 3);
559 /* Check the boot-source to disable bootdelay */
560 boot_device = env_get("boot_device");
561 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
562 env_set("bootdelay", "0");
564 #ifdef CONFIG_BOARD_EARLY_INIT_F
565 env_set_ulong("dh_som_rev", somcode);
566 env_set_ulong("dh_board_rev", brdcode);
567 env_set_ulong("dh_ddr3_code", ddr3code);
573 void board_quiesce_devices(void)
576 setup_led(LEDST_OFF);
580 /* eth init function : weak called in eqos driver */
581 int board_interface_eth_init(struct udevice *dev,
582 phy_interface_t interface_type)
586 bool eth_clk_sel_reg = false;
587 bool eth_ref_clk_sel_reg = false;
589 /* Gigabit Ethernet 125MHz clock selection. */
590 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
592 /* Ethernet 50Mhz RMII clock selection */
593 eth_ref_clk_sel_reg =
594 dev_read_bool(dev, "st,eth_ref_clk_sel");
596 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
601 switch (interface_type) {
602 case PHY_INTERFACE_MODE_MII:
603 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
604 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
605 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
607 case PHY_INTERFACE_MODE_GMII:
609 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
610 SYSCFG_PMCSETR_ETH_CLK_SEL;
612 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
613 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
615 case PHY_INTERFACE_MODE_RMII:
616 if (eth_ref_clk_sel_reg)
617 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
618 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
620 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
621 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
623 case PHY_INTERFACE_MODE_RGMII:
624 case PHY_INTERFACE_MODE_RGMII_ID:
625 case PHY_INTERFACE_MODE_RGMII_RXID:
626 case PHY_INTERFACE_MODE_RGMII_TXID:
628 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
629 SYSCFG_PMCSETR_ETH_CLK_SEL;
631 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
632 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
635 debug("%s: Do not manage %d interface\n",
636 __func__, interface_type);
637 /* Do not manage others interfaces */
641 /* clear and set ETH configuration bits */
642 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
643 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
644 syscfg + SYSCFG_PMCCLRR);
645 writel(value, syscfg + SYSCFG_PMCSETR);
650 enum env_location env_get_location(enum env_operation op, int prio)
655 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
656 return ENVL_SPI_FLASH;
662 #if defined(CONFIG_OF_BOARD_SETUP)
663 int ft_board_setup(void *blob, bd_t *bd)
669 static void board_copro_image_process(ulong fw_image, size_t fw_size)
671 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
673 if (!rproc_is_initialized())
675 printf("Remote Processor %d initialization failed\n",
680 ret = rproc_load(id, fw_image, fw_size);
681 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
682 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
686 env_set("copro_state", "booted");
690 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);