1 // SPDX-License-Identifier: GPL-2.0+
3 * DHCOM DH-iMX6 PDK board support
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
10 #include <dm/device-internal.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/mach-imx/sata.h>
24 #include <dwc_ahsata.h>
25 #include <environment.h>
27 #include <fsl_esdhc.h>
35 #include <usb/ehci-ci.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 #define I2C_PAD_CTRL \
40 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
43 #define EEPROM_I2C_ADDRESS 0x50
45 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
47 static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
49 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
50 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
51 .gp = IMX_GPIO_NR(3, 21)
54 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
55 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
56 .gp = IMX_GPIO_NR(3, 28)
60 static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
62 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
63 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
64 .gp = IMX_GPIO_NR(4, 12)
67 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
68 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
69 .gp = IMX_GPIO_NR(4, 13)
73 static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
75 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
76 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
77 .gp = IMX_GPIO_NR(1, 3)
80 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
81 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
82 .gp = IMX_GPIO_NR(1, 6)
86 static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
88 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
89 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
90 .gp = IMX_GPIO_NR(3, 21)
93 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
94 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
95 .gp = IMX_GPIO_NR(3, 28)
99 static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
101 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
102 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
103 .gp = IMX_GPIO_NR(4, 12)
106 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
107 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
108 .gp = IMX_GPIO_NR(4, 13)
112 static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
114 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
115 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
116 .gp = IMX_GPIO_NR(1, 3)
119 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
120 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
121 .gp = IMX_GPIO_NR(1, 6)
127 gd->ram_size = imx_ddr_size();
132 * Do not overwrite the console
133 * Use always serial for U-Boot console
135 int overwrite_console(void)
140 #ifdef CONFIG_FEC_MXC
141 static void eth_phy_reset(void)
144 gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
146 gpio_set_value(IMX_GPIO_NR(5, 0), 1);
149 gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
152 * KSZ9021 PHY needs at least 10 mSec after PHY reset
153 * is released to stabilize
158 static int setup_fec_clock(void)
160 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
162 /* set gpr1[21] to select anatop clock */
163 clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
165 return enable_fec_anatop_clock(0, ENET_50MHZ);
168 int board_eth_init(bd_t *bis)
170 uint32_t base = IMX_FEC_BASE;
171 struct mii_dev *bus = NULL;
172 struct phy_device *phydev = NULL;
174 gpio_request(IMX_GPIO_NR(5, 0), "PHY-reset");
175 gpio_request(IMX_GPIO_NR(1, 7), "VIO");
181 bus = fec_get_miibus(base, -1);
186 phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
188 printf("Ethernet PHY not found!\n");
192 return fec_probe(bis, -1, base, bus, phydev);
196 #ifdef CONFIG_USB_EHCI_MX6
197 static void setup_usb(void)
199 gpio_request(IMX_GPIO_NR(3, 31), "USB-VBUS");
201 * Set daisy chain for otg_pin_id on MX6Q.
202 * For MX6DL, this bit is reserved.
204 imx_iomux_set_gpr_register(1, 13, 1, 0);
207 int board_usb_phy_mode(int port)
210 return USB_INIT_HOST;
212 return USB_INIT_DEVICE;
215 int board_ehci_power(int port, int on)
221 gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
224 printf("MXC USB port %d not yet supported\n", port);
232 static int setup_dhcom_mac_from_fuse(void)
234 unsigned char enetaddr[6];
237 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
238 if (ret) /* ethaddr is already set */
241 imx_get_mac_from_fuse(0, enetaddr);
243 if (is_valid_ethaddr(enetaddr)) {
244 eth_env_set_enetaddr("ethaddr", enetaddr);
248 ret = i2c_set_bus_num(2);
250 printf("Error switching I2C bus!\n");
254 ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
256 printf("Error reading configuration EEPROM!\n");
260 if (is_valid_ethaddr(enetaddr))
261 eth_env_set_enetaddr("ethaddr", enetaddr);
266 int board_early_init_f(void)
268 #ifdef CONFIG_USB_EHCI_MX6
275 #ifdef CONFIG_MXC_SPI
276 int board_spi_cs_gpio(unsigned bus, unsigned cs)
278 if (bus == 0 && cs == 0)
279 return IMX_GPIO_NR(2, 30);
287 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
289 /* address of boot parameters */
290 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
292 /* Enable eim_slow clocks */
293 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
295 #ifdef CONFIG_SYS_I2C_MXC
297 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
298 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
299 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
301 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
302 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
303 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
307 setup_dhcom_mac_from_fuse();
312 #ifdef CONFIG_CMD_BMODE
313 static const struct boot_mode board_boot_modes[] = {
314 /* 4 bit bus width */
315 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
316 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
317 /* 8 bit bus width */
318 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
323 #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
324 #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
325 #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
327 static int board_get_hwcode(void)
331 gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
332 gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
333 gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
335 gpio_direction_input(HW_CODE_BIT_0);
336 gpio_direction_input(HW_CODE_BIT_1);
337 gpio_direction_input(HW_CODE_BIT_2);
339 /* HW 100 + HW 200 = 00b; HW 300 = 01b */
340 hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
341 (gpio_get_value(HW_CODE_BIT_1) << 1) |
342 gpio_get_value(HW_CODE_BIT_0)) + 2;
347 int board_late_init(void)
352 hw_code = board_get_hwcode();
354 switch (get_cpu_type()) {
355 case MXC_CPU_MX6SOLO:
356 snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
359 snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
362 snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
365 snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
368 snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
372 env_set("dhcom", buf);
374 #ifdef CONFIG_CMD_BMODE
375 add_board_boot_modes(board_boot_modes);
382 puts("Board: DHCOM i.MX6\n");