1 // SPDX-License-Identifier: GPL-2.0+
3 * DHCOM DH-iMX6 PDK board support
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
10 #include <dm/device-internal.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/sata.h>
23 #include <dwc_ahsata.h>
25 #include <environment.h>
27 #include <fsl_esdhc_imx.h>
29 #include <i2c_eeprom.h>
35 #include <usb/ehci-ci.h>
37 DECLARE_GLOBAL_DATA_PTR;
41 gd->ram_size = imx_ddr_size();
46 * Do not overwrite the console
47 * Use always serial for U-Boot console
49 int overwrite_console(void)
55 static void eth_phy_reset(void)
58 gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
60 gpio_set_value(IMX_GPIO_NR(5, 0), 1);
63 gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
66 * KSZ9021 PHY needs at least 10 mSec after PHY reset
67 * is released to stabilize
72 static int setup_fec_clock(void)
74 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
76 /* set gpr1[21] to select anatop clock */
77 clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
79 return enable_fec_anatop_clock(0, ENET_50MHZ);
82 int board_eth_init(bd_t *bis)
84 uint32_t base = IMX_FEC_BASE;
85 struct mii_dev *bus = NULL;
86 struct phy_device *phydev = NULL;
88 gpio_request(IMX_GPIO_NR(5, 0), "PHY-reset");
89 gpio_request(IMX_GPIO_NR(1, 7), "VIO");
95 bus = fec_get_miibus(base, -1);
100 phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
102 printf("Ethernet PHY not found!\n");
106 return fec_probe(bis, -1, base, bus, phydev);
110 #ifdef CONFIG_USB_EHCI_MX6
111 static void setup_usb(void)
114 * Set daisy chain for otg_pin_id on MX6Q.
115 * For MX6DL, this bit is reserved.
117 imx_iomux_set_gpr_register(1, 13, 1, 0);
120 int board_usb_phy_mode(int port)
123 return USB_INIT_HOST;
125 return USB_INIT_DEVICE;
129 static int setup_dhcom_mac_from_fuse(void)
133 unsigned char enetaddr[6];
136 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
137 if (ret) /* ethaddr is already set */
140 imx_get_mac_from_fuse(0, enetaddr);
142 if (is_valid_ethaddr(enetaddr)) {
143 eth_env_set_enetaddr("ethaddr", enetaddr);
147 eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
148 if (!ofnode_valid(eeprom)) {
149 printf("Invalid hardware path to EEPROM!\n");
153 ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
155 printf("Cannot find EEPROM!\n");
159 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
161 printf("Error reading configuration EEPROM!\n");
165 if (is_valid_ethaddr(enetaddr))
166 eth_env_set_enetaddr("ethaddr", enetaddr);
171 int board_early_init_f(void)
173 #ifdef CONFIG_USB_EHCI_MX6
182 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
184 /* address of boot parameters */
185 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
187 /* Enable eim_slow clocks */
188 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
190 setup_dhcom_mac_from_fuse();
195 #ifdef CONFIG_CMD_BMODE
196 static const struct boot_mode board_boot_modes[] = {
197 /* 4 bit bus width */
198 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
199 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
200 /* 8 bit bus width */
201 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
206 #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
207 #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
208 #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
210 static int board_get_hwcode(void)
214 gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
215 gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
216 gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
218 gpio_direction_input(HW_CODE_BIT_0);
219 gpio_direction_input(HW_CODE_BIT_1);
220 gpio_direction_input(HW_CODE_BIT_2);
222 /* HW 100 + HW 200 = 00b; HW 300 = 01b */
223 hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
224 (gpio_get_value(HW_CODE_BIT_1) << 1) |
225 gpio_get_value(HW_CODE_BIT_0)) + 2;
230 int board_late_init(void)
235 hw_code = board_get_hwcode();
237 switch (get_cpu_type()) {
238 case MXC_CPU_MX6SOLO:
239 snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
242 snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
245 snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
248 snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
251 snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
255 env_set("dhcom", buf);
257 #ifdef CONFIG_CMD_BMODE
258 add_board_boot_modes(board_boot_modes);
265 puts("Board: DHCOM i.MX6\n");
269 #ifdef CONFIG_MULTI_DTB_FIT
270 int board_fit_config_name_match(const char *name)
273 if (!strcmp(name, "imx6q-dhcom-pdk2"))
275 } else if (is_mx6sdl()) {
276 if (!strcmp(name, "imx6dl-dhcom-pdk2"))