board/cssi/MCR3000/MCR3000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2017 CS Systemes d'Information
   4  * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
   5  * Christophe Leroy <christophe.leroy@c-s.fr>
   6  *
   7  * Board specific routines for the MCR3000 board
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <mpc8xx.h>
  13 #include <fdt_support.h>
  14 #include <asm/io.h>
  15 #include <dm/uclass.h>
  16 #include <wdt.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #define SDRAM_MAX_SIZE                  (32 * 1024 * 1024)
  21
  22 static const uint cs1_dram_table_66[] = {
  23         /* DRAM - single read. (offset 0 in upm RAM) */
  24         0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
  25         0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  26
  27         /* DRAM - burst read. (offset 8 in upm RAM) */
  28         0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
  29         0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
  30         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  31         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  32
  33         /* DRAM - single write. (offset 18 in upm RAM) */
  34         0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
  35         0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  36
  37         /* DRAM - burst write. (offset 20 in upm RAM) */
  38         0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
  39         0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
  40         0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  41         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  42
  43         /* refresh  (offset 30 in upm RAM) */
  44         0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
  45         0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
  46
  47         /* init */
  48         0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
  49
  50         /* exception. (offset 3c in upm RAM) */
  51         0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  52 };
  53
  54 int ft_board_setup(void *blob, bd_t *bd)
  55 {
  56         const char *sync = "receive";
  57
  58         ft_cpu_setup(blob, bd);
  59
  60         /* BRG */
  61         do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
  62                              bd->bi_busfreq, 1);
  63
  64         /* MAC addr */
  65         fdt_fixup_ethernet(blob);
  66
  67         /* Bus Frequency for CPM */
  68         do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
  69
  70         /* E1 interface - Set data rate */
  71         do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
  72
  73         /* E1 interface - Set channel phase to 0 */
  74         do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
  75
  76         /* E1 interface - rising edge sync pulse transmit */
  77         do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
  78                          sync, strlen(sync), 1);
  79
  80         return 0;
  81 }
  82
  83 int checkboard(void)
  84 {
  85         serial_puts("BOARD: MCR3000 CSSI\n");
  86
  87         return 0;
  88 }
  89
  90 int dram_init(void)
  91 {
  92         immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  93         memctl8xx_t __iomem *memctl = &immap->im_memctl;
  94
  95         printf("UPMA init for SDRAM (CAS latency 2), ");
  96         printf("init address 0x%08x, size ", (int)dram_init);
  97         /* Configure UPMA for cs1 */
  98         upmconfig(UPMA, (uint *)cs1_dram_table_66,
  99                   sizeof(cs1_dram_table_66) / sizeof(uint));
 100         udelay(10);
 101         out_be16(&memctl->memc_mptpr, 0x0200);
 102         out_be32(&memctl->memc_mamr, 0x14904000);
 103         udelay(10);
 104         out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
 105         out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
 106         udelay(10);
 107         out_be32(&memctl->memc_mcr, 0x80002830);
 108         out_be32(&memctl->memc_mar, 0x00000088);
 109         out_be32(&memctl->memc_mcr, 0x80002038);
 110         udelay(200);
 111
 112         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 113                                     SDRAM_MAX_SIZE);
 114
 115         return 0;
 116 }
 117
 118 int misc_init_r(void)
 119 {
 120         immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 121         iop8xx_t __iomem *iop = &immr->im_ioport;
 122
 123         /* Set port C13 as GPIO (BTN_ACQ_AL) */
 124         clrbits_be16(&iop->iop_pcpar, 0x4);
 125         clrbits_be16(&iop->iop_pcdir, 0x4);
 126
 127         /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
 128         if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
 129                 env_set("bootdelay", "60");
 130
 131         return 0;
 132 }
 133
 134 int board_early_init_f(void)
 135 {
 136         immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 137
 138         /*
 139          * Erase FPGA(s) for reboot
 140          */
 141         clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
 142         setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
 143         udelay(1);                              /* Wait more than 300ns */
 144         setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
 145
 146         return 0;
 147 }
 148
 149 int board_early_init_r(void)
 150 {
 151         struct udevice *watchdog_dev = NULL;
 152
 153         if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 154                 puts("Cannot find watchdog!\n");
 155         } else {
 156                 puts("Enabling watchdog.\n");
 157                 wdt_start(watchdog_dev, 0xffff, 0);
 158         }
 159
 160         return 0;
 161 }