board/cssi/MCR3000/MCR3000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2017 CS Systemes d'Information
   4  * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
   5  * Christophe Leroy <christophe.leroy@c-s.fr>
   6  *
   7  * Board specific routines for the MCR3000 board
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <hwconfig.h>
  13 #include <mpc8xx.h>
  14 #include <fdt_support.h>
  15 #include <asm/io.h>
  16 #include <dm/uclass.h>
  17 #include <wdt.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define SDRAM_MAX_SIZE                  (32 * 1024 * 1024)
  22
  23 static const uint cs1_dram_table_66[] = {
  24         /* DRAM - single read. (offset 0 in upm RAM) */
  25         0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
  26         0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  27
  28         /* DRAM - burst read. (offset 8 in upm RAM) */
  29         0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
  30         0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
  31         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  32         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  33
  34         /* DRAM - single write. (offset 18 in upm RAM) */
  35         0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
  36         0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  37
  38         /* DRAM - burst write. (offset 20 in upm RAM) */
  39         0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
  40         0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
  41         0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  42         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  43
  44         /* refresh  (offset 30 in upm RAM) */
  45         0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
  46         0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
  47
  48         /* init */
  49         0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
  50
  51         /* exception. (offset 3c in upm RAM) */
  52         0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  53 };
  54
  55 int ft_board_setup(void *blob, bd_t *bd)
  56 {
  57         const char *sync = "receive";
  58
  59         ft_cpu_setup(blob, bd);
  60
  61         /* BRG */
  62         do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
  63                              bd->bi_busfreq, 1);
  64
  65         /* MAC addr */
  66         fdt_fixup_ethernet(blob);
  67
  68         /* Bus Frequency for CPM */
  69         do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
  70
  71         /* E1 interface - Set data rate */
  72         do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
  73
  74         /* E1 interface - Set channel phase to 0 */
  75         do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
  76
  77         /* E1 interface - rising edge sync pulse transmit */
  78         do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
  79                          sync, strlen(sync), 1);
  80
  81         return 0;
  82 }
  83
  84 int checkboard(void)
  85 {
  86         serial_puts("BOARD: MCR3000 CSSI\n");
  87
  88         return 0;
  89 }
  90
  91 int dram_init(void)
  92 {
  93         immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  94         memctl8xx_t __iomem *memctl = &immap->im_memctl;
  95
  96         printf("UPMA init for SDRAM (CAS latency 2), ");
  97         printf("init address 0x%08x, size ", (int)dram_init);
  98         /* Configure UPMA for cs1 */
  99         upmconfig(UPMA, (uint *)cs1_dram_table_66,
 100                   sizeof(cs1_dram_table_66) / sizeof(uint));
 101         udelay(10);
 102         out_be16(&memctl->memc_mptpr, 0x0200);
 103         out_be32(&memctl->memc_mamr, 0x14904000);
 104         udelay(10);
 105         out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
 106         out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
 107         udelay(10);
 108         out_be32(&memctl->memc_mcr, 0x80002830);
 109         out_be32(&memctl->memc_mar, 0x00000088);
 110         out_be32(&memctl->memc_mcr, 0x80002038);
 111         udelay(200);
 112
 113         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 114                                     SDRAM_MAX_SIZE);
 115
 116         return 0;
 117 }
 118
 119 int misc_init_r(void)
 120 {
 121         immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 122         iop8xx_t __iomem *iop = &immr->im_ioport;
 123
 124         /* Set port C13 as GPIO (BTN_ACQ_AL) */
 125         clrbits_be16(&iop->iop_pcpar, 0x4);
 126         clrbits_be16(&iop->iop_pcdir, 0x4);
 127
 128         /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
 129         if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
 130                 env_set("bootdelay", "60");
 131
 132         return 0;
 133 }
 134
 135 int board_early_init_f(void)
 136 {
 137         immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 138
 139         /*
 140          * Erase FPGA(s) for reboot
 141          */
 142         clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
 143         setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
 144         udelay(1);                              /* Wait more than 300ns */
 145         setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
 146
 147         return 0;
 148 }
 149
 150 int board_early_init_r(void)
 151 {
 152         struct udevice *watchdog_dev = NULL;
 153
 154         if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 155                 puts("Cannot find watchdog!\n");
 156         } else {
 157                 puts("Enabling watchdog.\n");
 158                 wdt_start(watchdog_dev, 0xffff, 0);
 159         }
 160
 161         return 0;
 162 }