1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2020 - Cortina Access Inc.
11 #include <linux/compiler.h>
12 #include <configs/presidio_asic.h>
13 #include <linux/psci.h>
16 #include <asm/armv8/mmu.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define CA_PERIPH_BASE 0xE0000000UL
21 #define CA_PERIPH_SIZE 0x20000000UL
22 #define CA_GLOBAL_BASE 0xf4320000
23 #define CA_GLOBAL_JTAG_ID 0xf4320000
24 #define CA_GLOBAL_BLOCK_RESET 0xf4320004
25 #define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16)
26 #define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94
27 #define CA_DMA_SEC_SSP_ID 0xf7001b80
29 int print_cpuinfo(void)
31 printf("CPU: Cortina Presidio G3\n");
35 static struct mm_region presidio_mem_map[] = {
39 .size = PHYS_SDRAM_1_SIZE,
40 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
44 .virt = CA_PERIPH_BASE,
45 .phys = CA_PERIPH_BASE,
46 .size = CA_PERIPH_SIZE,
47 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56 struct mm_region *mem_map = presidio_mem_map;
58 static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
61 asm volatile("mov x0, %0\n"
67 : "r" (arg0), "r" (arg1), "r" (arg2)
73 int board_early_init_r(void)
81 unsigned int reg_data, jtag_id;
84 writel(1, CONFIG_SYS_TIMER_BASE);
86 /* Enable snoop in CCI400 slave port#4 */
87 writel(3, 0xF5595000);
89 jtag_id = readl(CA_GLOBAL_JTAG_ID);
91 /* If this is HGU variant then do not use
92 * the Saturn daughter card ref. clk
94 if (jtag_id == 0x1010D8F3) {
95 reg_data = readl(0xF3100064);
96 /* change multifunc. REF CLK pin to
100 writel(reg_data, 0xf3100064);
108 unsigned int ddr_size;
110 ddr_size = readl(0x111100c);
111 gd->ram_size = ddr_size * 0x100000;
115 void reset_cpu(ulong addr)
117 invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
120 #ifdef CONFIG_LAST_STAGE_INIT
121 int last_stage_init(void)
125 val = readl(CA_GLOBAL_BLOCK_RESET);
126 val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA;
127 writel(val, CA_GLOBAL_BLOCK_RESET);
129 /* reduce output pclk ~3.7Hz to save power consumption */
130 writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL);