board/congatec/cgtqmx6eval/cgtqmx6eval.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  * Based on mx6qsabrelite.c file
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Leo Sartre, <lsartre@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/sata.h>
  19 #include <asm/imx-common/boot_mode.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <i2c.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze100_pmic.h>
  28 #include <linux/fb.h>
  29 #include <ipu_pixfmt.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  34         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  37         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  40         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  41         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  42         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  43
  44 #define MX6Q_QMX6_PFUZE_MUX             IMX_GPIO_NR(6, 9)
  45
  46 int dram_init(void)
  47 {
  48         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  49
  50         return 0;
  51 }
  52
  53 static iomux_v3_cfg_t const uart2_pads[] = {
  54         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  55         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  56 };
  57
  58 static iomux_v3_cfg_t const usdhc2_pads[] = {
  59         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66 };
  67
  68 static iomux_v3_cfg_t const usdhc3_pads[] = {
  69         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80 };
  81
  82 static iomux_v3_cfg_t const usdhc4_pads[] = {
  83         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  94 };
  95
  96 static iomux_v3_cfg_t const usb_otg_pads[] = {
  97         MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  98         MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  99 };
 100
 101 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 102 struct i2c_pads_info i2c_pad_info1 = {
 103         .scl = {
 104                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 105                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 106                 .gp = IMX_GPIO_NR(4, 12)
 107         },
 108         .sda = {
 109                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 110                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 111                 .gp = IMX_GPIO_NR(4, 13)
 112         }
 113 };
 114
 115 #define I2C_PMIC        1       /* I2C2 port is used to connect to the PMIC */
 116
 117 struct interface_level {
 118         char *name;
 119         uchar value;
 120 };
 121
 122 static struct interface_level mipi_levels[] = {
 123         {"0V0", 0x00},
 124         {"2V5", 0x17},
 125 };
 126
 127 /* setup board specific PMIC */
 128 int power_init_board(void)
 129 {
 130         struct pmic *p;
 131         u32 id1, id2, i;
 132         int ret;
 133         char const *lv_mipi;
 134
 135         /* configure I2C multiplexer */
 136         gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
 137
 138         power_pfuze100_init(I2C_PMIC);
 139         p = pmic_get("PFUZE100");
 140         if (!p)
 141                 return -EINVAL;
 142
 143         ret = pmic_probe(p);
 144         if (ret)
 145                 return ret;
 146
 147         pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
 148         pmic_reg_read(p, PFUZE100_REVID, &id2);
 149         printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
 150
 151         if (id2 >= 0x20)
 152                 return 0;
 153
 154         /* set level of MIPI if specified */
 155         lv_mipi = getenv("lv_mipi");
 156         if (lv_mipi)
 157                 return 0;
 158
 159         for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
 160                 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
 161                         printf("set MIPI level %s\n",
 162                                mipi_levels[i].name);
 163                         ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
 164                                              mipi_levels[i].value);
 165                         if (ret)
 166                                 return ret;
 167                 }
 168         }
 169
 170         return 0;
 171 }
 172
 173 static void setup_iomux_uart(void)
 174 {
 175         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 176 }
 177
 178 #ifdef CONFIG_FSL_ESDHC
 179 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 180         {USDHC2_BASE_ADDR},
 181         {USDHC3_BASE_ADDR},
 182         {USDHC4_BASE_ADDR},
 183 };
 184
 185 int board_mmc_getcd(struct mmc *mmc)
 186 {
 187         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 188         int ret = 0;
 189
 190         switch (cfg->esdhc_base) {
 191         case USDHC2_BASE_ADDR:
 192                 gpio_direction_input(IMX_GPIO_NR(1, 4));
 193                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 194                 break;
 195         case USDHC3_BASE_ADDR:
 196                 ret = 1;        /* eMMC is always present */
 197                 break;
 198         case USDHC4_BASE_ADDR:
 199                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 200                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 201                 break;
 202         default:
 203                 printf("Bad USDHC interface\n");
 204         }
 205
 206         return ret;
 207 }
 208
 209 int board_mmc_init(bd_t *bis)
 210 {
 211         s32 status = 0;
 212         int i;
 213
 214         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 215         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 216         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 217
 218         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 219         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 220         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 221
 222         for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
 223                 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 224                 if (status)
 225                         return status;
 226         }
 227
 228         return 0;
 229 }
 230 #endif
 231
 232 int board_ehci_hcd_init(int port)
 233 {
 234         switch (port) {
 235         case 0:
 236                 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 237                                                  ARRAY_SIZE(usb_otg_pads));
 238                 /*
 239                  * set daisy chain for otg_pin_id on 6q.
 240                  * for 6dl, this bit is reserved
 241                  */
 242                 imx_iomux_set_gpr_register(1, 13, 1, 1);
 243                 break;
 244         case 1:
 245                 /* nothing to do */
 246                 break;
 247         default:
 248                 printf("Invalid USB port: %d\n", port);
 249                 return -EINVAL;
 250         }
 251
 252         return 0;
 253 }
 254
 255 int board_ehci_power(int port, int on)
 256 {
 257         switch (port) {
 258         case 0:
 259                 break;
 260         case 1:
 261                 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
 262                 break;
 263         default:
 264                 printf("Invalid USB port: %d\n", port);
 265                 return -EINVAL;
 266         }
 267
 268         return 0;
 269 }
 270
 271 struct display_info_t {
 272         int bus;
 273         int addr;
 274         int pixfmt;
 275         int (*detect)(struct display_info_t const *dev);
 276         void (*enable)(struct display_info_t const *dev);
 277         struct fb_videomode mode;
 278 };
 279
 280 static void disable_lvds(struct display_info_t const *dev)
 281 {
 282         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 283
 284         clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 285                      IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 286 }
 287
 288 static void do_enable_hdmi(struct display_info_t const *dev)
 289 {
 290         disable_lvds(dev);
 291         imx_enable_hdmi_phy();
 292 }
 293
 294 static struct display_info_t const displays[] = {
 295 {
 296         .bus = -1,
 297         .addr = 0,
 298         .pixfmt = IPU_PIX_FMT_RGB666,
 299         .detect = NULL,
 300         .enable = NULL,
 301         .mode = {
 302                 .name =
 303                 "Hannstar-XGA",
 304                 .refresh = 60,
 305                 .xres = 1024,
 306                 .yres = 768,
 307                 .pixclock = 15385,
 308                 .left_margin = 220,
 309                 .right_margin = 40,
 310                 .upper_margin = 21,
 311                 .lower_margin = 7,
 312                 .hsync_len = 60,
 313                 .vsync_len = 10,
 314                 .sync = FB_SYNC_EXT,
 315                 .vmode = FB_VMODE_NONINTERLACED } },
 316 {
 317         .bus = -1,
 318         .addr = 0,
 319         .pixfmt = IPU_PIX_FMT_RGB24,
 320         .detect = NULL,
 321         .enable = do_enable_hdmi,
 322         .mode = {
 323                 .name = "HDMI",
 324                 .refresh = 60,
 325                 .xres = 1024,
 326                 .yres = 768,
 327                 .pixclock = 15385,
 328                 .left_margin = 220,
 329                 .right_margin = 40,
 330                 .upper_margin = 21,
 331                 .lower_margin = 7,
 332                 .hsync_len = 60,
 333                 .vsync_len = 10,
 334                 .sync = FB_SYNC_EXT,
 335                 .vmode = FB_VMODE_NONINTERLACED } }
 336 };
 337
 338 int board_video_skip(void)
 339 {
 340         int i;
 341         int ret;
 342         char const *panel = getenv("panel");
 343         if (!panel) {
 344                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 345                         struct display_info_t const *dev = displays + i;
 346                         if (dev->detect && dev->detect(dev)) {
 347                                 panel = dev->mode.name;
 348                                 printf("auto-detected panel %s\n", panel);
 349                                 break;
 350                         }
 351                 }
 352                 if (!panel) {
 353                         panel = displays[0].mode.name;
 354                         printf("No panel detected: default to %s\n", panel);
 355                         i = 0;
 356                 }
 357         } else {
 358                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 359                         if (!strcmp(panel, displays[i].mode.name))
 360                                 break;
 361                 }
 362         }
 363         if (i < ARRAY_SIZE(displays)) {
 364                 ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
 365                 if (!ret) {
 366                         if (displays[i].enable)
 367                                 displays[i].enable(displays + i);
 368                         printf("Display: %s (%ux%u)\n",
 369                                displays[i].mode.name, displays[i].mode.xres,
 370                                displays[i].mode.yres);
 371                 } else
 372                         printf("LCD %s cannot be configured: %d\n",
 373                                displays[i].mode.name, ret);
 374         } else {
 375                 printf("unsupported panel %s\n", panel);
 376                 return -EINVAL;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static void setup_display(void)
 383 {
 384         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 385         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 386         int reg;
 387
 388         enable_ipu_clock();
 389         imx_setup_hdmi();
 390
 391         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 392         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
 393                      MXC_CCM_CCGR3_LDB_DI1_MASK);
 394
 395         /* set LDB0, LDB1 clk select to 011/011 */
 396         reg = readl(&mxc_ccm->cs2cdr);
 397         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 398                  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 399         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 400                 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 401         writel(reg, &mxc_ccm->cs2cdr);
 402
 403         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
 404                      MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
 405
 406         setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
 407                      MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
 408                      CHSCCDR_CLK_SEL_LDB_DI0 <<
 409                      MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 410
 411         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 412                 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 413                 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 414                 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 415                 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 416                 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 417                 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 418                 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 419                 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 420         writel(reg, &iomux->gpr[2]);
 421
 422         reg = readl(&iomux->gpr[3]);
 423         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 424                        IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
 425                 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 426                  IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 427         writel(reg, &iomux->gpr[3]);
 428 }
 429
 430 /*
 431  * Do not overwrite the console
 432  * Use always serial for U-Boot console
 433  */
 434 int overwrite_console(void)
 435 {
 436         return 1;
 437 }
 438
 439 int board_early_init_f(void)
 440 {
 441         setup_iomux_uart();
 442         setup_display();
 443
 444         return 0;
 445 }
 446
 447 int board_init(void)
 448 {
 449         /* address of boot parameters */
 450         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 451
 452         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 453
 454 #ifdef CONFIG_CMD_SATA
 455         setup_sata();
 456 #endif
 457
 458         return 0;
 459 }
 460
 461 int checkboard(void)
 462 {
 463         puts("Board: Conga-QEVAL QMX6 Quad\n");
 464
 465         return 0;
 466 }
 467
 468 #ifdef CONFIG_CMD_BMODE
 469 static const struct boot_mode board_boot_modes[] = {
 470         /* 4 bit bus width */
 471         {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 472         {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 473         {NULL,          0},
 474 };
 475 #endif
 476
 477 int misc_init_r(void)
 478 {
 479 #ifdef CONFIG_CMD_BMODE
 480         add_board_boot_modes(board_boot_modes);
 481 #endif
 482         return 0;
 483 }