board/congatec/cgtqmx6eval/cgtqmx6eval.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   4  * Based on mx6qsabrelite.c file
   5  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   6  * Leo Sartre, <lsartre@adeneo-embedded.com>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/sata.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/mxc_i2c.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <env.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc_imx.h>
  28 #include <i2c.h>
  29 #include <input.h>
  30 #include <power/pmic.h>
  31 #include <power/pfuze100_pmic.h>
  32 #include <linux/fb.h>
  33 #include <ipu_pixfmt.h>
  34 #include <malloc.h>
  35 #include <miiphy.h>
  36 #include <netdev.h>
  37 #include <micrel.h>
  38 #include <spi_flash.h>
  39 #include <spi.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  44         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  47         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  50         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  51         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  52         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  53
  54 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  55         PAD_CTL_SPEED_MED |             \
  56         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  57
  58 #define MX6Q_QMX6_PFUZE_MUX             IMX_GPIO_NR(6, 9)
  59
  60
  61 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  63         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  64
  65 int dram_init(void)
  66 {
  67         gd->ram_size = imx_ddr_size();
  68
  69         return 0;
  70 }
  71
  72 static iomux_v3_cfg_t const uart2_pads[] = {
  73         IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  74         IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  75 };
  76
  77 #ifndef CONFIG_SPL_BUILD
  78 static iomux_v3_cfg_t const usdhc2_pads[] = {
  79         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  80         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  81         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  82         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  83         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86 };
  87
  88 static iomux_v3_cfg_t const usdhc3_pads[] = {
  89         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  96         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  97         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  98         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  99         IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 100 };
 101 #endif
 102
 103 static iomux_v3_cfg_t const usdhc4_pads[] = {
 104         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 105         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 106         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 107         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 108         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 109         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 110         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 111         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 112         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 113         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 114         IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 115 };
 116
 117 static iomux_v3_cfg_t const usb_otg_pads[] = {
 118         IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
 119         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
 120 };
 121
 122 static iomux_v3_cfg_t enet_pads_ksz9031[] = {
 123         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 124         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 125         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 126         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 127         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 128         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 129         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 130         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 131         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 132         IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 133         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 134         IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 135         IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 136         IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 137         IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 138 };
 139
 140 static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
 141         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 142         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 143         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 144         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 145         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 146         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 147 };
 148
 149 static iomux_v3_cfg_t enet_pads_ar8035[] = {
 150         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 151         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 152         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 153         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 154         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 155         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 156         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 157         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 158         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 159         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 160         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 161         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 162         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 163         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 164         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 165 };
 166
 167 static iomux_v3_cfg_t const ecspi1_pads[] = {
 168         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 169         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 170         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 171         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 172 };
 173
 174 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 175 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 176         .scl = {
 177                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 178                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 179                 .gp = IMX_GPIO_NR(4, 12)
 180         },
 181         .sda = {
 182                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 183                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 184                 .gp = IMX_GPIO_NR(4, 13)
 185         }
 186 };
 187
 188 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 189         .scl = {
 190                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 191                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 192                 .gp = IMX_GPIO_NR(4, 12)
 193         },
 194         .sda = {
 195                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 196                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 197                 .gp = IMX_GPIO_NR(4, 13)
 198         }
 199 };
 200
 201 #define I2C_PMIC        1       /* I2C2 port is used to connect to the PMIC */
 202
 203 struct interface_level {
 204         char *name;
 205         uchar value;
 206 };
 207
 208 static struct interface_level mipi_levels[] = {
 209         {"0V0", 0x00},
 210         {"2V5", 0x17},
 211 };
 212
 213 /* setup board specific PMIC */
 214 int power_init_board(void)
 215 {
 216         struct pmic *p;
 217         u32 id1, id2, i;
 218         int ret;
 219         char const *lv_mipi;
 220
 221         /* configure I2C multiplexer */
 222         gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
 223
 224         power_pfuze100_init(I2C_PMIC);
 225         p = pmic_get("PFUZE100");
 226         if (!p)
 227                 return -EINVAL;
 228
 229         ret = pmic_probe(p);
 230         if (ret)
 231                 return ret;
 232
 233         pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
 234         pmic_reg_read(p, PFUZE100_REVID, &id2);
 235         printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
 236
 237         if (id2 >= 0x20)
 238                 return 0;
 239
 240         /* set level of MIPI if specified */
 241         lv_mipi = env_get("lv_mipi");
 242         if (lv_mipi)
 243                 return 0;
 244
 245         for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
 246                 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
 247                         printf("set MIPI level %s\n", mipi_levels[i].name);
 248                         ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
 249                                              mipi_levels[i].value);
 250                         if (ret)
 251                                 return ret;
 252                 }
 253         }
 254
 255         return 0;
 256 }
 257
 258 int board_eth_init(bd_t *bis)
 259 {
 260         struct phy_device *phydev;
 261         struct mii_dev *bus;
 262         unsigned short id1, id2;
 263         int ret;
 264
 265         /* check whether KSZ9031 or AR8035 has to be configured */
 266         SETUP_IOMUX_PADS(enet_pads_ar8035);
 267
 268         /* phy reset */
 269         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 270         udelay(2000);
 271         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 272         udelay(500);
 273
 274         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 275         if (!bus)
 276                 return -EINVAL;
 277         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 278         if (!phydev) {
 279                 printf("Error: phy device not found.\n");
 280                 ret = -ENODEV;
 281                 goto free_bus;
 282         }
 283
 284         /* get the PHY id */
 285         id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
 286         id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
 287
 288         if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
 289                 /* re-configure for Micrel KSZ9031 */
 290                 printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
 291                        phydev->addr);
 292
 293                 /* phy reset: gpio3-23 */
 294                 gpio_set_value(IMX_GPIO_NR(3, 23), 0);
 295                 gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
 296                 gpio_set_value(IMX_GPIO_NR(6, 25), 1);
 297                 gpio_set_value(IMX_GPIO_NR(6, 27), 1);
 298                 gpio_set_value(IMX_GPIO_NR(6, 28), 1);
 299                 gpio_set_value(IMX_GPIO_NR(6, 29), 1);
 300                 SETUP_IOMUX_PADS(enet_pads_ksz9031);
 301                 gpio_set_value(IMX_GPIO_NR(6, 24), 1);
 302                 udelay(500);
 303                 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 304                 SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
 305         } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
 306                 /* configure Atheros AR8035 - actually nothing to do */
 307                 printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
 308                        phydev->addr);
 309         } else {
 310                 printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
 311                 ret = -EINVAL;
 312                 goto free_phydev;
 313         }
 314
 315         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 316         if (ret)
 317                 goto free_phydev;
 318
 319         return 0;
 320
 321 free_phydev:
 322         free(phydev);
 323 free_bus:
 324         free(bus);
 325         return ret;
 326 }
 327
 328 int mx6_rgmii_rework(struct phy_device *phydev)
 329 {
 330         unsigned short id1, id2;
 331         unsigned short val;
 332
 333         /* check whether KSZ9031 or AR8035 has to be configured */
 334         id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
 335         id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
 336
 337         if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
 338                 /* finalize phy configuration for Micrel KSZ9031 */
 339                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 340                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
 341                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 342                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
 343
 344                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 345                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
 346                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 347                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
 348
 349                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 350                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
 351                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 352                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
 353
 354                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 355                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
 356                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 357                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
 358
 359                 /* fix KSZ9031 link up issue */
 360                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
 361                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
 362                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
 363                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
 364                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
 365                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
 366                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
 367                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
 368         }
 369
 370         if ((id1 == 0x004d) && (id2 == 0xd072)) {
 371                 /* enable AR8035 ouput a 125MHz clk from CLK_25M */
 372                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
 373                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
 374                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
 375                 val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
 376                 val &= 0xfe63;
 377                 val |= 0x18;
 378                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
 379
 380                 /* introduce tx clock delay */
 381                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 382                 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 383                 val |= 0x0100;
 384                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 385
 386                 /* disable hibernation */
 387                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
 388                 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 389                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
 390         }
 391         return 0;
 392 }
 393
 394 int board_phy_config(struct phy_device *phydev)
 395 {
 396         mx6_rgmii_rework(phydev);
 397
 398         if (phydev->drv->config)
 399                 phydev->drv->config(phydev);
 400
 401         return 0;
 402 }
 403
 404 static void setup_iomux_uart(void)
 405 {
 406         SETUP_IOMUX_PADS(uart2_pads);
 407 }
 408
 409 #ifdef CONFIG_MXC_SPI
 410 static void setup_spi(void)
 411 {
 412         SETUP_IOMUX_PADS(ecspi1_pads);
 413         gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
 414 }
 415 #endif
 416
 417 #ifdef CONFIG_FSL_ESDHC_IMX
 418 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 419         {USDHC2_BASE_ADDR},
 420         {USDHC3_BASE_ADDR},
 421         {USDHC4_BASE_ADDR},
 422 };
 423
 424 int board_mmc_getcd(struct mmc *mmc)
 425 {
 426         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 427         int ret = 0;
 428
 429         switch (cfg->esdhc_base) {
 430         case USDHC2_BASE_ADDR:
 431                 gpio_direction_input(IMX_GPIO_NR(1, 4));
 432                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 433                 break;
 434         case USDHC3_BASE_ADDR:
 435                 ret = 1;        /* eMMC is always present */
 436                 break;
 437         case USDHC4_BASE_ADDR:
 438                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 439                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 440                 break;
 441         default:
 442                 printf("Bad USDHC interface\n");
 443         }
 444
 445         return ret;
 446 }
 447
 448 int board_mmc_init(bd_t *bis)
 449 {
 450 #ifndef CONFIG_SPL_BUILD
 451         s32 status = 0;
 452         int i;
 453
 454         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 455         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 456         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 457
 458         SETUP_IOMUX_PADS(usdhc2_pads);
 459         SETUP_IOMUX_PADS(usdhc3_pads);
 460         SETUP_IOMUX_PADS(usdhc4_pads);
 461
 462         for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
 463                 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 464                 if (status)
 465                         return status;
 466         }
 467
 468         return 0;
 469 #else
 470         SETUP_IOMUX_PADS(usdhc4_pads);
 471         usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 472         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 473         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 474
 475         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 476 #endif
 477 }
 478 #endif
 479
 480 int board_ehci_hcd_init(int port)
 481 {
 482         switch (port) {
 483         case 0:
 484                 SETUP_IOMUX_PADS(usb_otg_pads);
 485                 /*
 486                  * set daisy chain for otg_pin_id on 6q.
 487                  * for 6dl, this bit is reserved
 488                  */
 489                 imx_iomux_set_gpr_register(1, 13, 1, 1);
 490                 break;
 491         case 1:
 492                 /* nothing to do */
 493                 break;
 494         default:
 495                 printf("Invalid USB port: %d\n", port);
 496                 return -EINVAL;
 497         }
 498
 499         return 0;
 500 }
 501
 502 int board_ehci_power(int port, int on)
 503 {
 504         switch (port) {
 505         case 0:
 506                 break;
 507         case 1:
 508                 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
 509                 break;
 510         default:
 511                 printf("Invalid USB port: %d\n", port);
 512                 return -EINVAL;
 513         }
 514
 515         return 0;
 516 }
 517
 518 struct display_info_t {
 519         int bus;
 520         int addr;
 521         int pixfmt;
 522         int (*detect)(struct display_info_t const *dev);
 523         void (*enable)(struct display_info_t const *dev);
 524         struct fb_videomode mode;
 525 };
 526
 527 static void disable_lvds(struct display_info_t const *dev)
 528 {
 529         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 530
 531         clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 532                      IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 533 }
 534
 535 static void do_enable_hdmi(struct display_info_t const *dev)
 536 {
 537         disable_lvds(dev);
 538         imx_enable_hdmi_phy();
 539 }
 540
 541 static struct display_info_t const displays[] = {
 542 {
 543         .bus = -1,
 544         .addr = 0,
 545         .pixfmt = IPU_PIX_FMT_RGB666,
 546         .detect = NULL,
 547         .enable = NULL,
 548         .mode = {
 549                 .name =
 550                 "Hannstar-XGA",
 551                 .refresh = 60,
 552                 .xres = 1024,
 553                 .yres = 768,
 554                 .pixclock = 15385,
 555                 .left_margin = 220,
 556                 .right_margin = 40,
 557                 .upper_margin = 21,
 558                 .lower_margin = 7,
 559                 .hsync_len = 60,
 560                 .vsync_len = 10,
 561                 .sync = FB_SYNC_EXT,
 562                 .vmode = FB_VMODE_NONINTERLACED } },
 563 {
 564         .bus = -1,
 565         .addr = 0,
 566         .pixfmt = IPU_PIX_FMT_RGB24,
 567         .detect = NULL,
 568         .enable = do_enable_hdmi,
 569         .mode = {
 570                 .name = "HDMI",
 571                 .refresh = 60,
 572                 .xres = 1024,
 573                 .yres = 768,
 574                 .pixclock = 15385,
 575                 .left_margin = 220,
 576                 .right_margin = 40,
 577                 .upper_margin = 21,
 578                 .lower_margin = 7,
 579                 .hsync_len = 60,
 580                 .vsync_len = 10,
 581                 .sync = FB_SYNC_EXT,
 582                 .vmode = FB_VMODE_NONINTERLACED } }
 583 };
 584
 585 int board_video_skip(void)
 586 {
 587         int i;
 588         int ret;
 589         char const *panel = env_get("panel");
 590         if (!panel) {
 591                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 592                         struct display_info_t const *dev = displays + i;
 593                         if (dev->detect && dev->detect(dev)) {
 594                                 panel = dev->mode.name;
 595                                 printf("auto-detected panel %s\n", panel);
 596                                 break;
 597                         }
 598                 }
 599                 if (!panel) {
 600                         panel = displays[0].mode.name;
 601                         printf("No panel detected: default to %s\n", panel);
 602                         i = 0;
 603                 }
 604         } else {
 605                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 606                         if (!strcmp(panel, displays[i].mode.name))
 607                                 break;
 608                 }
 609         }
 610         if (i < ARRAY_SIZE(displays)) {
 611                 ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
 612                 if (!ret) {
 613                         if (displays[i].enable)
 614                                 displays[i].enable(displays + i);
 615                         printf("Display: %s (%ux%u)\n",
 616                                displays[i].mode.name, displays[i].mode.xres,
 617                                displays[i].mode.yres);
 618                 } else
 619                         printf("LCD %s cannot be configured: %d\n",
 620                                displays[i].mode.name, ret);
 621         } else {
 622                 printf("unsupported panel %s\n", panel);
 623                 return -EINVAL;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static void setup_display(void)
 630 {
 631         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 632         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 633         int reg;
 634
 635         enable_ipu_clock();
 636         imx_setup_hdmi();
 637
 638         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 639         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
 640                      MXC_CCM_CCGR3_LDB_DI1_MASK);
 641
 642         /* set LDB0, LDB1 clk select to 011/011 */
 643         reg = readl(&mxc_ccm->cs2cdr);
 644         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 645                  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 646         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 647                 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 648         writel(reg, &mxc_ccm->cs2cdr);
 649
 650         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
 651                      MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
 652
 653         setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
 654                      MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
 655                      CHSCCDR_CLK_SEL_LDB_DI0 <<
 656                      MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 657
 658         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 659                 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 660                 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 661                 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 662                 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 663                 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 664                 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 665                 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 666                 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 667         writel(reg, &iomux->gpr[2]);
 668
 669         reg = readl(&iomux->gpr[3]);
 670         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 671                        IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
 672                 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 673                  IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 674         writel(reg, &iomux->gpr[3]);
 675 }
 676
 677 /*
 678  * Do not overwrite the console
 679  * Use always serial for U-Boot console
 680  */
 681 int overwrite_console(void)
 682 {
 683         return 1;
 684 }
 685
 686 int board_early_init_f(void)
 687 {
 688         setup_iomux_uart();
 689 #ifdef CONFIG_MXC_SPI
 690         setup_spi();
 691 #endif
 692         return 0;
 693 }
 694
 695 int board_init(void)
 696 {
 697         /* address of boot parameters */
 698         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 699
 700
 701         if (is_mx6dq())
 702                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 703         else
 704                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 705
 706         setup_display();
 707
 708 #ifdef CONFIG_SATA
 709         setup_sata();
 710 #endif
 711
 712         return 0;
 713 }
 714
 715 int checkboard(void)
 716 {
 717         char *type = "unknown";
 718
 719         if (is_cpu_type(MXC_CPU_MX6Q))
 720                 type = "Quad";
 721         else if (is_cpu_type(MXC_CPU_MX6D))
 722                 type = "Dual";
 723         else if (is_cpu_type(MXC_CPU_MX6DL))
 724                 type = "Dual-Lite";
 725         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 726                 type = "Solo";
 727
 728         printf("Board: conga-QMX6 %s\n", type);
 729
 730         return 0;
 731 }
 732
 733 #ifdef CONFIG_MXC_SPI
 734 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 735 {
 736         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
 737 }
 738 #endif
 739
 740 #ifdef CONFIG_CMD_BMODE
 741 static const struct boot_mode board_boot_modes[] = {
 742         /* 4 bit bus width */
 743         {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 744         {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 745         {NULL,          0},
 746 };
 747 #endif
 748
 749 int misc_init_r(void)
 750 {
 751 #ifdef CONFIG_CMD_BMODE
 752         add_board_boot_modes(board_boot_modes);
 753 #endif
 754         return 0;
 755 }
 756
 757 int board_late_init(void)
 758 {
 759 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 760         if (is_mx6dq())
 761                 env_set("board_rev", "MX6Q");
 762         else
 763                 env_set("board_rev", "MX6DL");
 764 #endif
 765
 766         return 0;
 767 }
 768
 769 #ifdef CONFIG_SPL_BUILD
 770 #include <asm/arch/mx6-ddr.h>
 771 #include <spl.h>
 772 #include <linux/libfdt.h>
 773 #include <spi_flash.h>
 774 #include <spi.h>
 775
 776 const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 777         .dram_sdclk_0 =  0x00000030,
 778         .dram_sdclk_1 =  0x00000030,
 779         .dram_cas =  0x00000030,
 780         .dram_ras =  0x00000030,
 781         .dram_reset =  0x00000030,
 782         .dram_sdcke0 =  0x00003000,
 783         .dram_sdcke1 =  0x00003000,
 784         .dram_sdba2 =  0x00000000,
 785         .dram_sdodt0 =  0x00000030,
 786         .dram_sdodt1 =  0x00000030,
 787         .dram_sdqs0 =  0x00000030,
 788         .dram_sdqs1 =  0x00000030,
 789         .dram_sdqs2 =  0x00000030,
 790         .dram_sdqs3 =  0x00000030,
 791         .dram_sdqs4 =  0x00000030,
 792         .dram_sdqs5 =  0x00000030,
 793         .dram_sdqs6 =  0x00000030,
 794         .dram_sdqs7 =  0x00000030,
 795         .dram_dqm0 =  0x00000030,
 796         .dram_dqm1 =  0x00000030,
 797         .dram_dqm2 =  0x00000030,
 798         .dram_dqm3 =  0x00000030,
 799         .dram_dqm4 =  0x00000030,
 800         .dram_dqm5 =  0x00000030,
 801         .dram_dqm6 =  0x00000030,
 802         .dram_dqm7 =  0x00000030,
 803 };
 804
 805 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 806         .dram_sdclk_0 = 0x00000030,
 807         .dram_sdclk_1 = 0x00000030,
 808         .dram_cas =     0x00000030,
 809         .dram_ras =     0x00000030,
 810         .dram_reset =   0x00000030,
 811         .dram_sdcke0 =  0x00003000,
 812         .dram_sdcke1 =  0x00003000,
 813         .dram_sdba2 =   0x00000000,
 814         .dram_sdodt0 =  0x00000030,
 815         .dram_sdodt1 =  0x00000030,
 816         .dram_sdqs0 =   0x00000030,
 817         .dram_sdqs1 =   0x00000030,
 818         .dram_sdqs2 =   0x00000030,
 819         .dram_sdqs3 =   0x00000030,
 820         .dram_sdqs4 =   0x00000030,
 821         .dram_sdqs5 =   0x00000030,
 822         .dram_sdqs6 =   0x00000030,
 823         .dram_sdqs7 =   0x00000030,
 824         .dram_dqm0 =    0x00000030,
 825         .dram_dqm1 =    0x00000030,
 826         .dram_dqm2 =    0x00000030,
 827         .dram_dqm3 =    0x00000030,
 828         .dram_dqm4 =    0x00000030,
 829         .dram_dqm5 =    0x00000030,
 830         .dram_dqm6 =    0x00000030,
 831         .dram_dqm7 =    0x00000030,
 832 };
 833
 834 const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 835         .grp_ddr_type =  0x000C0000,
 836         .grp_ddrmode_ctl =  0x00020000,
 837         .grp_ddrpke =  0x00000000,
 838         .grp_addds =  0x00000030,
 839         .grp_ctlds =  0x00000030,
 840         .grp_ddrmode =  0x00020000,
 841         .grp_b0ds =  0x00000030,
 842         .grp_b1ds =  0x00000030,
 843         .grp_b2ds =  0x00000030,
 844         .grp_b3ds =  0x00000030,
 845         .grp_b4ds =  0x00000030,
 846         .grp_b5ds =  0x00000030,
 847         .grp_b6ds =  0x00000030,
 848         .grp_b7ds =  0x00000030,
 849 };
 850
 851 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 852         .grp_ddr_type = 0x000c0000,
 853         .grp_ddrmode_ctl = 0x00020000,
 854         .grp_ddrpke = 0x00000000,
 855         .grp_addds = 0x00000030,
 856         .grp_ctlds = 0x00000030,
 857         .grp_ddrmode = 0x00020000,
 858         .grp_b0ds = 0x00000030,
 859         .grp_b1ds = 0x00000030,
 860         .grp_b2ds = 0x00000030,
 861         .grp_b3ds = 0x00000030,
 862         .grp_b4ds = 0x00000030,
 863         .grp_b5ds = 0x00000030,
 864         .grp_b6ds = 0x00000030,
 865         .grp_b7ds = 0x00000030,
 866 };
 867
 868 const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
 869         .p0_mpwldectrl0 =  0x0016001A,
 870         .p0_mpwldectrl1 =  0x0023001C,
 871         .p1_mpwldectrl0 =  0x0028003A,
 872         .p1_mpwldectrl1 =  0x001F002C,
 873         .p0_mpdgctrl0 =  0x43440354,
 874         .p0_mpdgctrl1 =  0x033C033C,
 875         .p1_mpdgctrl0 =  0x43300368,
 876         .p1_mpdgctrl1 =  0x03500330,
 877         .p0_mprddlctl =  0x3228242E,
 878         .p1_mprddlctl =  0x2C2C2636,
 879         .p0_mpwrdlctl =  0x36323A38,
 880         .p1_mpwrdlctl =  0x42324440,
 881 };
 882
 883 const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 884         .p0_mpwldectrl0 =  0x00080016,
 885         .p0_mpwldectrl1 =  0x001D0016,
 886         .p1_mpwldectrl0 =  0x0018002C,
 887         .p1_mpwldectrl1 =  0x000D001D,
 888         .p0_mpdgctrl0 =    0x43200334,
 889         .p0_mpdgctrl1 =    0x0320031C,
 890         .p1_mpdgctrl0 =    0x0344034C,
 891         .p1_mpdgctrl1 =    0x03380314,
 892         .p0_mprddlctl =    0x3E36383A,
 893         .p1_mprddlctl =    0x38363240,
 894         .p0_mpwrdlctl =    0x36364238,
 895         .p1_mpwrdlctl =    0x4230423E,
 896 };
 897
 898 static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
 899         .p0_mpwldectrl0 =  0x00480049,
 900         .p0_mpwldectrl1 =  0x00410044,
 901         .p0_mpdgctrl0 =    0x42480248,
 902         .p0_mpdgctrl1 =    0x023C023C,
 903         .p0_mprddlctl =    0x40424644,
 904         .p0_mpwrdlctl =    0x34323034,
 905 };
 906
 907 const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
 908         .p0_mpwldectrl0 =  0x0043004B,
 909         .p0_mpwldectrl1 =  0x003A003E,
 910         .p1_mpwldectrl0 =  0x0047004F,
 911         .p1_mpwldectrl1 =  0x004E0061,
 912         .p0_mpdgctrl0 =    0x42500250,
 913         .p0_mpdgctrl1 =    0x0238023C,
 914         .p1_mpdgctrl0 =    0x42640264,
 915         .p1_mpdgctrl1 =    0x02500258,
 916         .p0_mprddlctl =    0x40424846,
 917         .p1_mprddlctl =    0x46484842,
 918         .p0_mpwrdlctl =    0x38382C30,
 919         .p1_mpwrdlctl =    0x34343430,
 920 };
 921
 922 static struct mx6_ddr3_cfg mem_ddr_2g = {
 923         .mem_speed = 1600,
 924         .density = 2,
 925         .width = 16,
 926         .banks = 8,
 927         .rowaddr = 14,
 928         .coladdr = 10,
 929         .pagesz = 2,
 930         .trcd = 1310,
 931         .trcmin = 4875,
 932         .trasmin = 3500,
 933 };
 934
 935 static struct mx6_ddr3_cfg mem_ddr_4g = {
 936         .mem_speed = 1600,
 937         .density = 4,
 938         .width = 16,
 939         .banks = 8,
 940         .rowaddr = 15,
 941         .coladdr = 10,
 942         .pagesz = 2,
 943         .trcd = 1310,
 944         .trcmin = 4875,
 945         .trasmin = 3500,
 946 };
 947
 948 static void ccgr_init(void)
 949 {
 950         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 951
 952         writel(0x00C03F3F, &ccm->CCGR0);
 953         writel(0x0030FC03, &ccm->CCGR1);
 954         writel(0x0FFFC000, &ccm->CCGR2);
 955         writel(0x3FF00000, &ccm->CCGR3);
 956         writel(0x00FFF300, &ccm->CCGR4);
 957         writel(0x0F0000C3, &ccm->CCGR5);
 958         writel(0x000003FF, &ccm->CCGR6);
 959 }
 960
 961 /* Define a minimal structure so that the part number can be read via SPL */
 962 struct mfgdata {
 963         unsigned char tsize;
 964         /* size of checksummed part in bytes */
 965         unsigned char ckcnt;
 966         /* checksum corrected byte */
 967         unsigned char cksum;
 968         /* decimal serial number, packed BCD */
 969         unsigned char serial[6];
 970          /* part number, right justified, ASCII */
 971         unsigned char pn[16];
 972 };
 973
 974 static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
 975 {
 976         int remain = len;
 977         unsigned char *sptr = src;
 978         unsigned char *dptr = dst;
 979
 980         while (remain) {
 981                 if (*sptr) {
 982                         *dptr = *sptr;
 983                         dptr++;
 984                 }
 985                 sptr++;
 986                 remain--;
 987         }
 988         *dptr = 0x0;
 989 }
 990
 991 #define CFG_MFG_ADDR_OFFSET     (spi->size - SZ_16K)
 992 static bool is_2gb(void)
 993 {
 994         struct spi_flash *spi;
 995         int ret;
 996         char buf[sizeof(struct mfgdata)];
 997         struct mfgdata *data = (struct mfgdata *)buf;
 998         unsigned char outbuf[32];
 999
1000         spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
1001                               CONFIG_ENV_SPI_CS,
1002                               CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
1003         ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
1004                              buf);
1005         if (ret)
1006                 return false;
1007
1008         /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
1009         conv_ascii(outbuf, data->pn, sizeof(data->pn));
1010         if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
1011                 return true;
1012         else
1013                 return false;
1014 }
1015
1016 static void spl_dram_init(int width)
1017 {
1018         struct mx6_ddr_sysinfo sysinfo = {
1019                 /* width of data bus:0=16,1=32,2=64 */
1020                 .dsize = width / 32,
1021                 /* config for full 4GB range so that get_mem_size() works */
1022                 .cs_density = 32, /* 32Gb per CS */
1023                 /* single chip select */
1024                 .ncs = 1,
1025                 .cs1_mirror = 0,
1026                 .rtt_wr = 2,
1027                 .rtt_nom = 2,
1028                 .walat = 0,
1029                 .ralat = 5,
1030                 .mif3_mode = 3,
1031                 .bi_on = 1,
1032                 .sde_to_rst = 0x0d,
1033                 .rst_to_cke = 0x20,
1034                 .refsel = 1,    /* Refresh cycles at 32KHz */
1035                 .refr = 7,      /* 8 refresh commands per refresh cycle */
1036         };
1037
1038         if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
1039                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1040                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
1041                 return;
1042         }
1043
1044         if (is_mx6dq()) {
1045                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1046                 mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
1047         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
1048                 sysinfo.walat = 1;
1049                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1050                 mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
1051         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
1052                 sysinfo.walat = 1;
1053                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1054                 mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
1055         }
1056 }
1057
1058 void board_init_f(ulong dummy)
1059 {
1060         /* setup AIPS and disable watchdog */
1061         arch_cpu_init();
1062
1063         ccgr_init();
1064         gpr_init();
1065
1066         /* iomux and setup of i2c */
1067         board_early_init_f();
1068
1069         /* setup GP timer */
1070         timer_init();
1071
1072         /* UART clocks enabled and gd valid - init serial console */
1073         preloader_console_init();
1074
1075         /* Needed for malloc() to work in SPL prior to board_init_r() */
1076         spl_init();
1077
1078         /* DDR initialization */
1079         if (is_cpu_type(MXC_CPU_MX6SOLO))
1080                 spl_dram_init(32);
1081         else
1082                 spl_dram_init(64);
1083
1084         /* Clear the BSS. */
1085         memset(__bss_start, 0, __bss_end - __bss_start);
1086
1087         /* load/boot image from boot device */
1088         board_init_r(NULL, 0);
1089 }
1090 #endif