board/compulab/cm_t43/cm_t43.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Compulab, Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <miiphy.h>
   9 #include <cpsw.h>
  10 #include <net.h>
  11 #include <asm/gpio.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/emif.h>
  14 #include <linux/delay.h>
  15 #include <power/pmic.h>
  16 #include <power/tps65218.h>
  17 #include "board.h"
  18 #include <usb.h>
  19 #include <asm/omap_common.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  24
  25 /* setup board specific PMIC */
  26 int power_init_board(void)
  27 {
  28         struct pmic *p;
  29         uchar tps_status = 0;
  30
  31         power_tps65218_init(I2C_PMIC);
  32         p = pmic_get("TPS65218_PMIC");
  33         if (p && !pmic_probe(p)) {
  34                 puts("PMIC:  TPS65218\n");
  35                 /* We don't care if fseal is locked, but we do need it set */
  36                 tps65218_lock_fseal();
  37                 tps65218_reg_read(TPS65218_STATUS, &tps_status);
  38                 if (!(tps_status & TPS65218_FSEAL))
  39                         printf("WARNING: RTC not backed by battery!\n");
  40         }
  41
  42         return 0;
  43 }
  44
  45 int board_init(void)
  46 {
  47         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  48         gpmc_init();
  49         set_i2c_pin_mux();
  50         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  51         i2c_probe(TPS65218_CHIP_PM);
  52
  53         return 0;
  54 }
  55
  56 int board_usb_init(int index, enum usb_init_type init)
  57 {
  58         enable_usb_clocks(index);
  59         return 0;
  60 }
  61
  62 int board_usb_cleanup(int index, enum usb_init_type init)
  63 {
  64         disable_usb_clocks(index);
  65         return 0;
  66 }
  67
  68 #ifdef CONFIG_DRIVER_TI_CPSW
  69
  70 static void cpsw_control(int enabled)
  71 {
  72         return;
  73 }
  74
  75 static struct cpsw_slave_data cpsw_slaves[] = {
  76         {
  77                 .slave_reg_ofs  = 0x208,
  78                 .sliver_reg_ofs = 0xd80,
  79                 .phy_addr       = 0,
  80                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
  81         },
  82         {
  83                 .slave_reg_ofs  = 0x308,
  84                 .sliver_reg_ofs = 0xdc0,
  85                 .phy_addr       = 1,
  86                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
  87         },
  88 };
  89
  90 static struct cpsw_platform_data cpsw_data = {
  91         .mdio_base              = CPSW_MDIO_BASE,
  92         .cpsw_base              = CPSW_BASE,
  93         .mdio_div               = 0xff,
  94         .channels               = 8,
  95         .cpdma_reg_ofs          = 0x800,
  96         .slaves                 = 2,
  97         .slave_data             = cpsw_slaves,
  98         .ale_reg_ofs            = 0xd00,
  99         .ale_entries            = 1024,
 100         .host_port_reg_ofs      = 0x108,
 101         .hw_stats_reg_ofs       = 0x900,
 102         .bd_ram_ofs             = 0x2000,
 103         .mac_control            = (1 << 5),
 104         .control                = cpsw_control,
 105         .host_port_num          = 0,
 106         .version                = CPSW_CTRL_VERSION_2,
 107 };
 108
 109 #define GPIO_PHY1_RST           170
 110 #define GPIO_PHY2_RST           168
 111
 112 int board_phy_config(struct phy_device *phydev)
 113 {
 114         unsigned short val;
 115
 116         /* introduce tx clock delay */
 117         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 118         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 119         val |= 0x0100;
 120         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 121
 122         if (phydev->drv->config)
 123                 return phydev->drv->config(phydev);
 124
 125         return 0;
 126 }
 127
 128 static void board_phy_init(void)
 129 {
 130         set_mdio_pin_mux();
 131         writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
 132         writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
 133         writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
 134
 135         /* For revision A */
 136         writel(0x2000009, 0x44df2e6c);
 137         writel(0x38a, 0x44df2e70);
 138
 139         mdelay(10);
 140
 141         gpio_request(GPIO_PHY1_RST, "phy1_rst");
 142         gpio_request(GPIO_PHY2_RST, "phy2_rst");
 143         gpio_direction_output(GPIO_PHY1_RST, 0);
 144         gpio_direction_output(GPIO_PHY2_RST, 0);
 145         mdelay(2);
 146
 147         gpio_set_value(GPIO_PHY1_RST, 1);
 148         gpio_set_value(GPIO_PHY2_RST, 1);
 149         mdelay(2);
 150 }
 151
 152 int board_eth_init(bd_t *bis)
 153 {
 154         int rv;
 155
 156         set_rgmii_pin_mux();
 157         writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 158         board_phy_init();
 159
 160         rv = cpsw_register(&cpsw_data);
 161         if (rv < 0)
 162                 printf("Error %d registering CPSW switch\n", rv);
 163
 164         return rv;
 165 }
 166 #endif