board/compulab/cm_t335/cm_t335.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for Compulab CM-T335 board
   4  *
   5  * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
   6  *
   7  * Author: Ilya Ledvich <ilya@compulab.co.il>
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <errno.h>
  13 #include <miiphy.h>
  14 #include <net.h>
  15 #include <status_led.h>
  16 #include <cpsw.h>
  17
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/hardware_am33xx.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22
  23 #include "../common/eeprom.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /*
  28  * Basic board specific setup.  Pinmux has been handled already.
  29  */
  30 int board_init(void)
  31 {
  32         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  33
  34         gpmc_init();
  35
  36 #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  37         status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
  38 #endif
  39         return 0;
  40 }
  41
  42 #if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
  43 static void cpsw_control(int enabled)
  44 {
  45         /* VTP can be added here */
  46         return;
  47 }
  48
  49 static struct cpsw_slave_data cpsw_slave = {
  50         .slave_reg_ofs  = 0x208,
  51         .sliver_reg_ofs = 0xd80,
  52         .phy_addr       = 0,
  53         .phy_if         = PHY_INTERFACE_MODE_RGMII,
  54 };
  55
  56 static struct cpsw_platform_data cpsw_data = {
  57         .mdio_base              = CPSW_MDIO_BASE,
  58         .cpsw_base              = CPSW_BASE,
  59         .mdio_div               = 0xff,
  60         .channels               = 8,
  61         .cpdma_reg_ofs          = 0x800,
  62         .slaves                 = 1,
  63         .slave_data             = &cpsw_slave,
  64         .ale_reg_ofs            = 0xd00,
  65         .ale_entries            = 1024,
  66         .host_port_reg_ofs      = 0x108,
  67         .hw_stats_reg_ofs       = 0x900,
  68         .bd_ram_ofs             = 0x2000,
  69         .mac_control            = (1 << 5),
  70         .control                = cpsw_control,
  71         .host_port_num          = 0,
  72         .version                = CPSW_CTRL_VERSION_2,
  73 };
  74
  75 /* PHY reset GPIO */
  76 #define GPIO_PHY_RST            GPIO_PIN(3, 7)
  77
  78 static void board_phy_init(void)
  79 {
  80         gpio_request(GPIO_PHY_RST, "phy_rst");
  81         gpio_direction_output(GPIO_PHY_RST, 0);
  82         mdelay(2);
  83         gpio_set_value(GPIO_PHY_RST, 1);
  84         mdelay(2);
  85 }
  86
  87 static void get_efuse_mac_addr(uchar *enetaddr)
  88 {
  89         uint32_t mac_hi, mac_lo;
  90         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  91
  92         mac_lo = readl(&cdev->macid0l);
  93         mac_hi = readl(&cdev->macid0h);
  94         enetaddr[0] = mac_hi & 0xFF;
  95         enetaddr[1] = (mac_hi & 0xFF00) >> 8;
  96         enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
  97         enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
  98         enetaddr[4] = mac_lo & 0xFF;
  99         enetaddr[5] = (mac_lo & 0xFF00) >> 8;
 100 }
 101
 102 /*
 103  * Routine: handle_mac_address
 104  * Description: prepare MAC address for on-board Ethernet.
 105  */
 106 static int handle_mac_address(void)
 107 {
 108         uchar enetaddr[6];
 109         int rv;
 110
 111         rv = eth_env_get_enetaddr("ethaddr", enetaddr);
 112         if (rv)
 113                 return 0;
 114
 115         rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
 116         if (rv)
 117                 get_efuse_mac_addr(enetaddr);
 118
 119         if (!is_valid_ethaddr(enetaddr))
 120                 return -1;
 121
 122         return eth_env_set_enetaddr("ethaddr", enetaddr);
 123 }
 124
 125 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 126 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 127 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 128 #define AR8051_RGMII_TX_CLK_DLY         0x100
 129
 130 int board_eth_init(bd_t *bis)
 131 {
 132         int rv, n = 0;
 133         const char *devname;
 134         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 135
 136         rv = handle_mac_address();
 137         if (rv)
 138                 printf("No MAC address found!\n");
 139
 140         writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 141
 142         board_phy_init();
 143
 144         rv = cpsw_register(&cpsw_data);
 145         if (rv < 0)
 146                 printf("Error %d registering CPSW switch\n", rv);
 147         else
 148                 n += rv;
 149
 150         /*
 151          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 152          * operating points.  So we must set the TX clock delay feature
 153          * in the AR8051 PHY.  Since we only support a single ethernet
 154          * device, we only do this for the first instance.
 155          */
 156         devname = miiphy_get_current_dev();
 157
 158         miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 159                      AR8051_DEBUG_RGMII_CLK_DLY_REG);
 160         miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 161                      AR8051_RGMII_TX_CLK_DLY);
 162         return n;
 163 }
 164 #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */