board/ccv/xpress/xpress.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   4  */
   5
   6 #include <init.h>
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/mx6ul_pins.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/io.h>
  20 #include <common.h>
  21 #include <env.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <mmc.h>
  26 #include <netdev.h>
  27 #include <usb.h>
  28 #include <usb/ehci-ci.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  33         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  34         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  37         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  38         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  41         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  42         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  43         PAD_CTL_ODE)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  46         PAD_CTL_SPEED_HIGH   |                                  \
  47         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  48
  49 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  50         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  51
  52 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  53
  54 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  55         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  56
  57 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |                \
  59         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |                       \
  60         PAD_CTL_SRE_FAST)
  61
  62 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  63
  64 static struct i2c_pads_info i2c_pad_info1 = {
  65         .scl = {
  66                 .i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  67                 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  68                 .gp = IMX_GPIO_NR(1, 2),
  69         },
  70         .sda = {
  71                 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  72                 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  73                 .gp = IMX_GPIO_NR(1, 3),
  74         },
  75 };
  76
  77 static struct i2c_pads_info i2c_pad_info2 = {
  78         .scl = {
  79                 .i2c_mode =  MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
  80                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
  81                 .gp = IMX_GPIO_NR(1, 0),
  82         },
  83         .sda = {
  84                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
  85                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
  86                 .gp = IMX_GPIO_NR(1, 1),
  87         },
  88 };
  89
  90 static struct i2c_pads_info i2c_pad_info4 = {
  91         .scl = {
  92                 .i2c_mode =  MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
  93                 .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
  94                 .gp = IMX_GPIO_NR(1, 20),
  95         },
  96         .sda = {
  97                 .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
  98                 .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
  99                 .gp = IMX_GPIO_NR(1, 21),
 100         },
 101 };
 102
 103 int dram_init(void)
 104 {
 105         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 106
 107         return 0;
 108 }
 109
 110 static iomux_v3_cfg_t const uart1_pads[] = {
 111         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 112         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 113         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 114         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 115 };
 116
 117 static iomux_v3_cfg_t const uart4_pads[] = {
 118         MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 119         MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 120 };
 121
 122 static iomux_v3_cfg_t const uart5_pads[] = {
 123         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 124         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 125         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 126         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 127 };
 128
 129 static iomux_v3_cfg_t const uart7_pads[] = {
 130         MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 131         MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 132 };
 133
 134 static iomux_v3_cfg_t const uart8_pads[] = {
 135         MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 136         MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 137 };
 138
 139 static void setup_iomux_uart(void)
 140 {
 141         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 142         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 143         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 144         imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
 145         imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
 146 }
 147
 148 /* eMMC on USDHC2 */
 149 static iomux_v3_cfg_t const usdhc2_pads[] = {
 150         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158         MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159         MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160
 161         /*
 162          * RST_B
 163          */
 164         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 165 };
 166
 167 static struct fsl_esdhc_cfg usdhc_cfg = {
 168         .esdhc_base = USDHC2_BASE_ADDR,
 169         .max_bus_width = 8,
 170 };
 171
 172 #define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
 173
 174 int board_mmc_getcd(struct mmc *mmc)
 175 {
 176         /* eMMC is always present */
 177         return 1;
 178 }
 179
 180 int board_mmc_init(bd_t *bis)
 181 {
 182         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 183
 184         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 185
 186         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 187 }
 188
 189 #define USB_OTHERREGS_OFFSET    0x800
 190 #define UCTRL_PWR_POL           (1 << 9)
 191
 192 static iomux_v3_cfg_t const usb_otg_pads[] = {
 193         /* OTG1 */
 194         MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 195         MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 196         /* OTG2 */
 197         MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 198         MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 199 };
 200
 201 static void setup_usb(void)
 202 {
 203         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 204                                          ARRAY_SIZE(usb_otg_pads));
 205 }
 206
 207 int board_usb_phy_mode(int port)
 208 {
 209         if (port == 1)
 210                 return USB_INIT_HOST;
 211         else
 212                 return usb_phy_mode(port);
 213 }
 214
 215 int board_ehci_hcd_init(int port)
 216 {
 217         u32 *usbnc_usb_ctrl;
 218
 219         if (port > 1)
 220                 return -EINVAL;
 221
 222         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 223                                  port * 4);
 224
 225         /* Set Power polarity */
 226         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 227
 228         return 0;
 229 }
 230
 231 static iomux_v3_cfg_t const fec1_pads[] = {
 232         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 233         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 236         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 237         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 238         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 239         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 240         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 241         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 242
 243         /* ENET1 reset */
 244         MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
 245         /* ENET1 interrupt */
 246         MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 247 };
 248
 249 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
 250
 251 int board_eth_init(bd_t *bis)
 252 {
 253         int ret;
 254
 255         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 256
 257         /* Reset LAN8742 PHY */
 258         ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
 259         if (!ret)
 260                 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
 261         mdelay(10);
 262         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 263         mdelay(10);
 264
 265         return cpu_eth_init(bis);
 266 }
 267
 268 static int setup_fec(int fec_id)
 269 {
 270         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 271         int ret;
 272
 273         /*
 274          * Use 50M anatop loopback REF_CLK1 for ENET1,
 275          * clear gpr1[13], set gpr1[17].
 276          */
 277         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 278                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 279
 280         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 281         if (ret)
 282                 return ret;
 283
 284         enable_enet_clk(1);
 285
 286         return 0;
 287 }
 288
 289 int board_phy_config(struct phy_device *phydev)
 290 {
 291         if (phydev->drv->config)
 292                 phydev->drv->config(phydev);
 293
 294         return 0;
 295 }
 296
 297 int board_early_init_f(void)
 298 {
 299         setup_iomux_uart();
 300
 301         return 0;
 302 }
 303
 304 int board_init(void)
 305 {
 306         /* Address of boot parameters */
 307         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 308
 309         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 310         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 311         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 312
 313         setup_fec(CONFIG_FEC_ENET_DEV);
 314
 315         setup_usb();
 316
 317         return 0;
 318 }
 319
 320 static const struct boot_mode board_boot_modes[] = {
 321         /* 8 bit bus width */
 322         {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
 323         { NULL, 0 },
 324 };
 325
 326 int board_late_init(void)
 327 {
 328         add_board_boot_modes(board_boot_modes);
 329         env_set("board_name", "xpress");
 330
 331         return 0;
 332 }
 333
 334 int checkboard(void)
 335 {
 336         puts("Board: CCV-EVA xPress\n");
 337
 338         return 0;
 339 }