board/ccv/xpress/xpress.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   4  */
   5
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/iomux.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/mx6ul_pins.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <asm/mach-imx/mxc_i2c.h>
  17 #include <asm/io.h>
  18 #include <common.h>
  19 #include <fsl_esdhc_imx.h>
  20 #include <i2c.h>
  21 #include <miiphy.h>
  22 #include <mmc.h>
  23 #include <netdev.h>
  24 #include <usb.h>
  25 #include <usb/ehci-ci.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  30         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  31         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  34         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  35         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  38         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  39         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  40         PAD_CTL_ODE)
  41
  42 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  43         PAD_CTL_SPEED_HIGH   |                                  \
  44         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  45
  46 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  47         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  48
  49 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  50
  51 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  52         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  53
  54 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  55         PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |                \
  56         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |                       \
  57         PAD_CTL_SRE_FAST)
  58
  59 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  60
  61 static struct i2c_pads_info i2c_pad_info1 = {
  62         .scl = {
  63                 .i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  64                 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  65                 .gp = IMX_GPIO_NR(1, 2),
  66         },
  67         .sda = {
  68                 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  69                 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  70                 .gp = IMX_GPIO_NR(1, 3),
  71         },
  72 };
  73
  74 static struct i2c_pads_info i2c_pad_info2 = {
  75         .scl = {
  76                 .i2c_mode =  MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
  77                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
  78                 .gp = IMX_GPIO_NR(1, 0),
  79         },
  80         .sda = {
  81                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
  82                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
  83                 .gp = IMX_GPIO_NR(1, 1),
  84         },
  85 };
  86
  87 static struct i2c_pads_info i2c_pad_info4 = {
  88         .scl = {
  89                 .i2c_mode =  MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
  90                 .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
  91                 .gp = IMX_GPIO_NR(1, 20),
  92         },
  93         .sda = {
  94                 .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
  95                 .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
  96                 .gp = IMX_GPIO_NR(1, 21),
  97         },
  98 };
  99
 100 int dram_init(void)
 101 {
 102         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 103
 104         return 0;
 105 }
 106
 107 static iomux_v3_cfg_t const uart1_pads[] = {
 108         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 109         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 110         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 111         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 112 };
 113
 114 static iomux_v3_cfg_t const uart4_pads[] = {
 115         MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 116         MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 117 };
 118
 119 static iomux_v3_cfg_t const uart5_pads[] = {
 120         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 121         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 122         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 123         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 124 };
 125
 126 static iomux_v3_cfg_t const uart7_pads[] = {
 127         MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 128         MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 129 };
 130
 131 static iomux_v3_cfg_t const uart8_pads[] = {
 132         MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 133         MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 134 };
 135
 136 static void setup_iomux_uart(void)
 137 {
 138         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 139         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 140         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 141         imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
 142         imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
 143 }
 144
 145 /* eMMC on USDHC2 */
 146 static iomux_v3_cfg_t const usdhc2_pads[] = {
 147         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157
 158         /*
 159          * RST_B
 160          */
 161         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 162 };
 163
 164 static struct fsl_esdhc_cfg usdhc_cfg = {
 165         .esdhc_base = USDHC2_BASE_ADDR,
 166         .max_bus_width = 8,
 167 };
 168
 169 #define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
 170
 171 int board_mmc_getcd(struct mmc *mmc)
 172 {
 173         /* eMMC is always present */
 174         return 1;
 175 }
 176
 177 int board_mmc_init(bd_t *bis)
 178 {
 179         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 180
 181         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 182
 183         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 184 }
 185
 186 #define USB_OTHERREGS_OFFSET    0x800
 187 #define UCTRL_PWR_POL           (1 << 9)
 188
 189 static iomux_v3_cfg_t const usb_otg_pads[] = {
 190         /* OTG1 */
 191         MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 192         MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 193         /* OTG2 */
 194         MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 195         MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 196 };
 197
 198 static void setup_usb(void)
 199 {
 200         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 201                                          ARRAY_SIZE(usb_otg_pads));
 202 }
 203
 204 int board_usb_phy_mode(int port)
 205 {
 206         if (port == 1)
 207                 return USB_INIT_HOST;
 208         else
 209                 return usb_phy_mode(port);
 210 }
 211
 212 int board_ehci_hcd_init(int port)
 213 {
 214         u32 *usbnc_usb_ctrl;
 215
 216         if (port > 1)
 217                 return -EINVAL;
 218
 219         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 220                                  port * 4);
 221
 222         /* Set Power polarity */
 223         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 224
 225         return 0;
 226 }
 227
 228 static iomux_v3_cfg_t const fec1_pads[] = {
 229         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 230         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 231         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 235         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 236         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 237         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 238         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 239
 240         /* ENET1 reset */
 241         MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
 242         /* ENET1 interrupt */
 243         MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 244 };
 245
 246 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
 247
 248 int board_eth_init(bd_t *bis)
 249 {
 250         int ret;
 251
 252         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 253
 254         /* Reset LAN8742 PHY */
 255         ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
 256         if (!ret)
 257                 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
 258         mdelay(10);
 259         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 260         mdelay(10);
 261
 262         return cpu_eth_init(bis);
 263 }
 264
 265 static int setup_fec(int fec_id)
 266 {
 267         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 268         int ret;
 269
 270         /*
 271          * Use 50M anatop loopback REF_CLK1 for ENET1,
 272          * clear gpr1[13], set gpr1[17].
 273          */
 274         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 275                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 276
 277         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 278         if (ret)
 279                 return ret;
 280
 281         enable_enet_clk(1);
 282
 283         return 0;
 284 }
 285
 286 int board_phy_config(struct phy_device *phydev)
 287 {
 288         if (phydev->drv->config)
 289                 phydev->drv->config(phydev);
 290
 291         return 0;
 292 }
 293
 294 int board_early_init_f(void)
 295 {
 296         setup_iomux_uart();
 297
 298         return 0;
 299 }
 300
 301 int board_init(void)
 302 {
 303         /* Address of boot parameters */
 304         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 305
 306         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 307         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 308         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 309
 310         setup_fec(CONFIG_FEC_ENET_DEV);
 311
 312         setup_usb();
 313
 314         return 0;
 315 }
 316
 317 static const struct boot_mode board_boot_modes[] = {
 318         /* 8 bit bus width */
 319         {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
 320         { NULL, 0 },
 321 };
 322
 323 int board_late_init(void)
 324 {
 325         add_board_boot_modes(board_boot_modes);
 326         env_set("board_name", "xpress");
 327
 328         return 0;
 329 }
 330
 331 int checkboard(void)
 332 {
 333         puts("Board: CCV-EVA xPress\n");
 334
 335         return 0;
 336 }