board/bticino/mamoj/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
   4  * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
   5  * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <serial.h>
  11 #include <spl.h>
  12
  13 #include <asm/io.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-ddr.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/arch/sys_proto.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define IMX6SDL_DRIVE_STRENGTH          0x28
  26 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  27                         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  28
  29 static iomux_v3_cfg_t const uart3_pads[] = {
  30         IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31         IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  32 };
  33
  34 #ifdef CONFIG_SPL_OS_BOOT
  35 int spl_start_uboot(void)
  36 {
  37         /* break into full u-boot on 'c' */
  38         if (serial_tstc() && serial_getc() == 'c')
  39                 return 1;
  40
  41         return 0;
  42 }
  43 #endif
  44
  45 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  46         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  47         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  48         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  49         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  50         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  51         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  52         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  53         .dram_sdba2 = 0x00000000,
  54         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  55         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  56         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  57         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  58         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  59         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  60         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  61         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  62         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  63         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  64         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  65         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  66         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  67         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  68         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  69         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  70         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  71         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  72 };
  73
  74 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  75         .grp_ddr_type = 0x000c0000,
  76         .grp_ddrmode_ctl = 0x00020000,
  77         .grp_ddrpke = 0x00000000,
  78         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  79         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  80         .grp_ddrmode = 0x00020000,
  81         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  82         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  83         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  84         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  85         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  86         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  87         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  88         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  89 };
  90
  91 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  92         .mem_speed = 1600,
  93         .density = 4,
  94         .width = 32,
  95         .banks = 8,
  96         .rowaddr = 14,
  97         .coladdr = 10,
  98         .pagesz = 2,
  99         .trcd = 1375,
 100         .trcmin = 4875,
 101         .trasmin = 3500,
 102         .SRT = 0,
 103 };
 104
 105 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 106         .p0_mpwldectrl0 = 0x0042004b,
 107         .p0_mpwldectrl1 = 0x0038003c,
 108         .p0_mpdgctrl0 = 0x42340230,
 109         .p0_mpdgctrl1 = 0x0228022c,
 110         .p0_mprddlctl = 0x42444646,
 111         .p0_mpwrdlctl = 0x38382e2e,
 112 };
 113
 114 static struct mx6_ddr_sysinfo mem_dl = {
 115         .dsize          = 1,
 116         .cs1_mirror     = 0,
 117         /* config for full 4GB range so that get_mem_size() works */
 118         .cs_density     = 32,
 119         .ncs            = 1,
 120         .bi_on          = 1,
 121         .rtt_nom        = 1,
 122         .rtt_wr         = 1,
 123         .ralat          = 5,
 124         .walat          = 0,
 125         .mif3_mode      = 3,
 126         .rst_to_cke     = 0x23,
 127         .sde_to_rst     = 0x10,
 128         .refsel         = 1,
 129         .refr           = 7,
 130 };
 131
 132 static void spl_dram_init(void)
 133 {
 134         mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 135         mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
 136
 137         udelay(100);
 138 }
 139
 140 static void ccgr_init(void)
 141 {
 142         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 143
 144         writel(0x00003f3f, &ccm->CCGR0);
 145         writel(0x0030fc00, &ccm->CCGR1);
 146         writel(0x000fc000, &ccm->CCGR2);
 147         writel(0x3f300000, &ccm->CCGR3);
 148         writel(0xff00f300, &ccm->CCGR4);
 149         writel(0x0f0000c3, &ccm->CCGR5);
 150         writel(0x000003cc, &ccm->CCGR6);
 151 }
 152
 153 void board_init_f(ulong dummy)
 154 {
 155         ccgr_init();
 156
 157         /* setup AIPS and disable watchdog */
 158         arch_cpu_init();
 159
 160         gpr_init();
 161
 162         /* iomux */
 163         SETUP_IOMUX_PADS(uart3_pads);
 164
 165         /* setup GP timer */
 166         timer_init();
 167
 168         /* UART clocks enabled and gd valid - init serial console */
 169         preloader_console_init();
 170
 171         /* DDR initialization */
 172         spl_dram_init();
 173 }