board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <malloc.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <linux/errno.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <asm/mach-imx/sata.h>
  24 #include <asm/mach-imx/spi.h>
  25 #include <asm/mach-imx/boot_mode.h>
  26 #include <asm/mach-imx/video.h>
  27 #include <mmc.h>
  28 #include <fsl_esdhc_imx.h>
  29 #include <micrel.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/crm_regs.h>
  33 #include <asm/arch/mxc_hdmi.h>
  34 #include <i2c.h>
  35 #include <input.h>
  36 #include <netdev.h>
  37 #include <usb/ehci-ci.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  41
  42 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  47         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  52
  53 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  54         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  55
  56 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  62
  63 #define RGB_PAD_CTRL    PAD_CTL_DSE_120ohm
  64
  65 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  66         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  67         PAD_CTL_SRE_SLOW)
  68
  69 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  70         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  71         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  72
  73 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  74
  75 /* Prevent compiler error if gpio number 08 or 09 is used */
  76 #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  77
  78 #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,             \
  79                 sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) {                \
  80         .scl = {                                                               \
  81                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  82                                          pad_ctrl),                            \
  83                 .gpio_mode = NEW_PAD_CTRL(                                     \
  84                         cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  85                         pad_ctrl),                                             \
  86                 .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp))                 \
  87         },                                                                     \
  88         .sda = {                                                               \
  89                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  90                                          pad_ctrl),                            \
  91                 .gpio_mode = NEW_PAD_CTRL(                                     \
  92                         cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  93                         pad_ctrl),                                             \
  94                         .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp))         \
  95         }                                                                      \
  96 }
  97
  98 #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,              \
  99                 sda_pad, sda_bank, sda_gp, pad_ctrl)                           \
 100                 _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,     \
 101                                 sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
 102
 103 #if defined(CONFIG_MX6QDL)
 104 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 105                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 106         I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp,      \
 107                 sda_pad, sda_bank, sda_gp, pad_ctrl),                   \
 108         I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp,     \
 109                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 110 #define I2C_PADS_INFO_ENTRY_SPACING 2
 111
 112 #define IOMUX_PAD_CTRL(name, pad_ctrl) \
 113                 NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl),        \
 114                 NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
 115 #else
 116 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 117                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 118         I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp,       \
 119                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 120 #define I2C_PADS_INFO_ENTRY_SPACING 1
 121
 122 #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
 123 #endif
 124
 125 int dram_init(void)
 126 {
 127         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 128
 129         return 0;
 130 }
 131
 132 static iomux_v3_cfg_t const uart1_pads[] = {
 133         IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
 134         IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
 135 };
 136
 137 static iomux_v3_cfg_t const uart2_pads[] = {
 138         IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
 139         IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
 140 };
 141
 142 static struct i2c_pads_info i2c_pads[] = {
 143         /* I2C1, SGTL5000 */
 144         I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
 145         /* I2C2 Camera, MIPI */
 146         I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
 147                             I2C_PAD_CTRL),
 148         /* I2C3, J15 - RGB connector */
 149         I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
 150 };
 151
 152 #define I2C_BUS_CNT    3
 153
 154 static iomux_v3_cfg_t const usdhc2_pads[] = {
 155         IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
 156         IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
 157         IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
 158         IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
 159         IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
 160         IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
 161 };
 162
 163 static iomux_v3_cfg_t const usdhc3_pads[] = {
 164         IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
 165         IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
 166         IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
 167         IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
 168         IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
 169         IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
 170         IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
 171 };
 172
 173 static iomux_v3_cfg_t const usdhc4_pads[] = {
 174         IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
 175         IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
 176         IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
 177         IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
 178         IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
 179         IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
 180         IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
 181 };
 182
 183 static iomux_v3_cfg_t const enet_pads1[] = {
 184         IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
 185         IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
 186         IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
 187         IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
 188         IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
 189         IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
 190         IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
 191         IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
 192         IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
 193         /* pin 35 - 1 (PHY_AD2) on reset */
 194         IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
 195         /* pin 32 - 1 - (MODE0) all */
 196         IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
 197         /* pin 31 - 1 - (MODE1) all */
 198         IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
 199         /* pin 28 - 1 - (MODE2) all */
 200         IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
 201         /* pin 27 - 1 - (MODE3) all */
 202         IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
 203         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 204         IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
 205         /* pin 42 PHY nRST */
 206         IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
 207         IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
 208 };
 209
 210 static iomux_v3_cfg_t const enet_pads2[] = {
 211         IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
 212         IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
 213         IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
 214         IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
 215         IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
 216         IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
 217 };
 218
 219 static iomux_v3_cfg_t const misc_pads[] = {
 220         IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
 221         IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
 222         IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
 223         /* OTG Power enable */
 224         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 225 };
 226
 227 /* wl1271 pads on nitrogen6x */
 228 static iomux_v3_cfg_t const wl12xx_pads[] = {
 229         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 230         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 231         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 232 };
 233 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 234 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 235 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 236
 237 /* Button assignments for J14 */
 238 static iomux_v3_cfg_t const button_pads[] = {
 239         /* Menu */
 240         IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
 241         /* Back */
 242         IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
 243         /* Labelled Search (mapped to Power under Android) */
 244         IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
 245         /* Home */
 246         IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
 247         /* Volume Down */
 248         IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
 249         /* Volume Up */
 250         IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
 251 };
 252
 253 static void setup_iomux_enet(void)
 254 {
 255         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 256         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 257         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 258         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 259         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 260         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 261         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 262         SETUP_IOMUX_PADS(enet_pads1);
 263         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 264
 265         /* Need delay 10ms according to KSZ9021 spec */
 266         udelay(1000 * 10);
 267         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 268         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 269
 270         SETUP_IOMUX_PADS(enet_pads2);
 271         udelay(100);    /* Wait 100 us before using mii interface */
 272 }
 273
 274 static iomux_v3_cfg_t const usb_pads[] = {
 275         IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
 276 };
 277
 278 static void setup_iomux_uart(void)
 279 {
 280         SETUP_IOMUX_PADS(uart1_pads);
 281         SETUP_IOMUX_PADS(uart2_pads);
 282 }
 283
 284 #ifdef CONFIG_USB_EHCI_MX6
 285 int board_ehci_hcd_init(int port)
 286 {
 287         SETUP_IOMUX_PADS(usb_pads);
 288
 289         /* Reset USB hub */
 290         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 291         mdelay(2);
 292         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 293
 294         return 0;
 295 }
 296
 297 int board_ehci_power(int port, int on)
 298 {
 299         if (port)
 300                 return 0;
 301         gpio_set_value(GP_USB_OTG_PWR, on);
 302         return 0;
 303 }
 304
 305 #endif
 306
 307 #ifdef CONFIG_FSL_ESDHC_IMX
 308 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 309         {USDHC3_BASE_ADDR},
 310         {USDHC4_BASE_ADDR},
 311 };
 312
 313 int board_mmc_getcd(struct mmc *mmc)
 314 {
 315         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 316         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 317                         IMX_GPIO_NR(2, 6);
 318
 319         gpio_direction_input(gp_cd);
 320         return !gpio_get_value(gp_cd);
 321 }
 322
 323 int board_mmc_init(bd_t *bis)
 324 {
 325         int ret;
 326         u32 index = 0;
 327
 328         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 329         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 330
 331         usdhc_cfg[0].max_bus_width = 4;
 332         usdhc_cfg[1].max_bus_width = 4;
 333
 334         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 335                 switch (index) {
 336                 case 0:
 337                         SETUP_IOMUX_PADS(usdhc3_pads);
 338                         break;
 339                 case 1:
 340                        SETUP_IOMUX_PADS(usdhc4_pads);
 341                        break;
 342                 default:
 343                        printf("Warning: you configured more USDHC controllers"
 344                                "(%d) then supported by the board (%d)\n",
 345                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 346                        return -EINVAL;
 347                 }
 348
 349                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 350                 if (ret)
 351                         return ret;
 352         }
 353
 354         return 0;
 355 }
 356 #endif
 357
 358 #ifdef CONFIG_MXC_SPI
 359 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 360 {
 361         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 362 }
 363
 364 static iomux_v3_cfg_t const ecspi1_pads[] = {
 365         /* SS1 */
 366         IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
 367         IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
 368         IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
 369         IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
 370 };
 371
 372 static void setup_spi(void)
 373 {
 374         SETUP_IOMUX_PADS(ecspi1_pads);
 375 }
 376 #endif
 377
 378 int board_phy_config(struct phy_device *phydev)
 379 {
 380         /* min rx data delay */
 381         ksz9021_phy_extended_write(phydev,
 382                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 383         /* min tx data delay */
 384         ksz9021_phy_extended_write(phydev,
 385                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 386         /* max rx/tx clock delay, min rx/tx control */
 387         ksz9021_phy_extended_write(phydev,
 388                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 389         if (phydev->drv->config)
 390                 phydev->drv->config(phydev);
 391
 392         return 0;
 393 }
 394
 395 int board_eth_init(bd_t *bis)
 396 {
 397         uint32_t base = IMX_FEC_BASE;
 398         struct mii_dev *bus = NULL;
 399         struct phy_device *phydev = NULL;
 400         int ret;
 401
 402         gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
 403         gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
 404         gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
 405         gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
 406         gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
 407         gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
 408         gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
 409         gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
 410         gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
 411         setup_iomux_enet();
 412
 413 #ifdef CONFIG_FEC_MXC
 414         bus = fec_get_miibus(base, -1);
 415         if (!bus)
 416                 return -EINVAL;
 417         /* scan phy 4,5,6,7 */
 418         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 419         if (!phydev) {
 420                 ret = -EINVAL;
 421                 goto free_bus;
 422         }
 423         printf("using phy at %d\n", phydev->addr);
 424         ret  = fec_probe(bis, -1, base, bus, phydev);
 425         if (ret)
 426                 goto free_phydev;
 427 #endif
 428
 429 #ifdef CONFIG_CI_UDC
 430         /* For otg ethernet*/
 431         usb_eth_initialize(bis);
 432 #endif
 433         return 0;
 434
 435 free_phydev:
 436         free(phydev);
 437 free_bus:
 438         free(bus);
 439         return ret;
 440 }
 441
 442 static void setup_buttons(void)
 443 {
 444         SETUP_IOMUX_PADS(button_pads);
 445 }
 446
 447 #if defined(CONFIG_VIDEO_IPUV3)
 448
 449 static iomux_v3_cfg_t const backlight_pads[] = {
 450         /* Backlight on RGB connector: J15 */
 451         IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
 452 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 453
 454         /* Backlight on LVDS connector: J6 */
 455         IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
 456 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 457 };
 458
 459 static iomux_v3_cfg_t const rgb_pads[] = {
 460         IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
 461         IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
 462         IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
 463         IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
 464         IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
 465         IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
 466         IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
 467         IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
 468         IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
 469         IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
 470         IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
 471         IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
 472         IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
 473         IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
 474         IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
 475         IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
 476         IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
 477         IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
 478         IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
 479         IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
 480         IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
 481         IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
 482         IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
 483         IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
 484         IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
 485         IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
 486         IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
 487         IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
 488         IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
 489 };
 490
 491 static void do_enable_hdmi(struct display_info_t const *dev)
 492 {
 493         imx_enable_hdmi_phy();
 494 }
 495
 496 static int detect_i2c(struct display_info_t const *dev)
 497 {
 498         return ((0 == i2c_set_bus_num(dev->bus))
 499                 &&
 500                 (0 == i2c_probe(dev->addr)));
 501 }
 502
 503 static void enable_lvds(struct display_info_t const *dev)
 504 {
 505         struct iomuxc *iomux = (struct iomuxc *)
 506                                 IOMUXC_BASE_ADDR;
 507         u32 reg = readl(&iomux->gpr[2]);
 508         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 509         writel(reg, &iomux->gpr[2]);
 510         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 511 }
 512
 513 static void enable_lvds_jeida(struct display_info_t const *dev)
 514 {
 515         struct iomuxc *iomux = (struct iomuxc *)
 516                                 IOMUXC_BASE_ADDR;
 517         u32 reg = readl(&iomux->gpr[2]);
 518         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 519              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 520         writel(reg, &iomux->gpr[2]);
 521         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 522 }
 523
 524 static void enable_rgb(struct display_info_t const *dev)
 525 {
 526         SETUP_IOMUX_PADS(rgb_pads);
 527         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 528 }
 529
 530 struct display_info_t const displays[] = {{
 531         .bus    = 1,
 532         .addr   = 0x50,
 533         .pixfmt = IPU_PIX_FMT_RGB24,
 534         .detect = detect_i2c,
 535         .enable = do_enable_hdmi,
 536         .mode   = {
 537                 .name           = "HDMI",
 538                 .refresh        = 60,
 539                 .xres           = 1024,
 540                 .yres           = 768,
 541                 .pixclock       = 15385,
 542                 .left_margin    = 220,
 543                 .right_margin   = 40,
 544                 .upper_margin   = 21,
 545                 .lower_margin   = 7,
 546                 .hsync_len      = 60,
 547                 .vsync_len      = 10,
 548                 .sync           = FB_SYNC_EXT,
 549                 .vmode          = FB_VMODE_NONINTERLACED
 550 } }, {
 551         .bus    = 0,
 552         .addr   = 0,
 553         .pixfmt = IPU_PIX_FMT_RGB24,
 554         .detect = NULL,
 555         .enable = enable_lvds_jeida,
 556         .mode   = {
 557                 .name           = "LDB-WXGA",
 558                 .refresh        = 60,
 559                 .xres           = 1280,
 560                 .yres           = 800,
 561                 .pixclock       = 14065,
 562                 .left_margin    = 40,
 563                 .right_margin   = 40,
 564                 .upper_margin   = 3,
 565                 .lower_margin   = 80,
 566                 .hsync_len      = 10,
 567                 .vsync_len      = 10,
 568                 .sync           = FB_SYNC_EXT,
 569                 .vmode          = FB_VMODE_NONINTERLACED
 570 } }, {
 571         .bus    = 0,
 572         .addr   = 0,
 573         .pixfmt = IPU_PIX_FMT_RGB24,
 574         .detect = NULL,
 575         .enable = enable_lvds,
 576         .mode   = {
 577                 .name           = "LDB-WXGA-S",
 578                 .refresh        = 60,
 579                 .xres           = 1280,
 580                 .yres           = 800,
 581                 .pixclock       = 14065,
 582                 .left_margin    = 40,
 583                 .right_margin   = 40,
 584                 .upper_margin   = 3,
 585                 .lower_margin   = 80,
 586                 .hsync_len      = 10,
 587                 .vsync_len      = 10,
 588                 .sync           = FB_SYNC_EXT,
 589                 .vmode          = FB_VMODE_NONINTERLACED
 590 } }, {
 591         .bus    = 2,
 592         .addr   = 0x4,
 593         .pixfmt = IPU_PIX_FMT_LVDS666,
 594         .detect = detect_i2c,
 595         .enable = enable_lvds,
 596         .mode   = {
 597                 .name           = "Hannstar-XGA",
 598                 .refresh        = 60,
 599                 .xres           = 1024,
 600                 .yres           = 768,
 601                 .pixclock       = 15385,
 602                 .left_margin    = 220,
 603                 .right_margin   = 40,
 604                 .upper_margin   = 21,
 605                 .lower_margin   = 7,
 606                 .hsync_len      = 60,
 607                 .vsync_len      = 10,
 608                 .sync           = FB_SYNC_EXT,
 609                 .vmode          = FB_VMODE_NONINTERLACED
 610 } }, {
 611         .bus    = 0,
 612         .addr   = 0,
 613         .pixfmt = IPU_PIX_FMT_LVDS666,
 614         .detect = NULL,
 615         .enable = enable_lvds,
 616         .mode   = {
 617                 .name           = "LG-9.7",
 618                 .refresh        = 60,
 619                 .xres           = 1024,
 620                 .yres           = 768,
 621                 .pixclock       = 15385, /* ~65MHz */
 622                 .left_margin    = 480,
 623                 .right_margin   = 260,
 624                 .upper_margin   = 16,
 625                 .lower_margin   = 6,
 626                 .hsync_len      = 250,
 627                 .vsync_len      = 10,
 628                 .sync           = FB_SYNC_EXT,
 629                 .vmode          = FB_VMODE_NONINTERLACED
 630 } }, {
 631         .bus    = 2,
 632         .addr   = 0x38,
 633         .pixfmt = IPU_PIX_FMT_LVDS666,
 634         .detect = detect_i2c,
 635         .enable = enable_lvds,
 636         .mode   = {
 637                 .name           = "wsvga-lvds",
 638                 .refresh        = 60,
 639                 .xres           = 1024,
 640                 .yres           = 600,
 641                 .pixclock       = 15385,
 642                 .left_margin    = 220,
 643                 .right_margin   = 40,
 644                 .upper_margin   = 21,
 645                 .lower_margin   = 7,
 646                 .hsync_len      = 60,
 647                 .vsync_len      = 10,
 648                 .sync           = FB_SYNC_EXT,
 649                 .vmode          = FB_VMODE_NONINTERLACED
 650 } }, {
 651         .bus    = 2,
 652         .addr   = 0x10,
 653         .pixfmt = IPU_PIX_FMT_RGB666,
 654         .detect = detect_i2c,
 655         .enable = enable_rgb,
 656         .mode   = {
 657                 .name           = "fusion7",
 658                 .refresh        = 60,
 659                 .xres           = 800,
 660                 .yres           = 480,
 661                 .pixclock       = 33898,
 662                 .left_margin    = 96,
 663                 .right_margin   = 24,
 664                 .upper_margin   = 3,
 665                 .lower_margin   = 10,
 666                 .hsync_len      = 72,
 667                 .vsync_len      = 7,
 668                 .sync           = 0x40000002,
 669                 .vmode          = FB_VMODE_NONINTERLACED
 670 } }, {
 671         .bus    = 0,
 672         .addr   = 0,
 673         .pixfmt = IPU_PIX_FMT_RGB666,
 674         .detect = NULL,
 675         .enable = enable_rgb,
 676         .mode   = {
 677                 .name           = "svga",
 678                 .refresh        = 60,
 679                 .xres           = 800,
 680                 .yres           = 600,
 681                 .pixclock       = 15385,
 682                 .left_margin    = 220,
 683                 .right_margin   = 40,
 684                 .upper_margin   = 21,
 685                 .lower_margin   = 7,
 686                 .hsync_len      = 60,
 687                 .vsync_len      = 10,
 688                 .sync           = 0,
 689                 .vmode          = FB_VMODE_NONINTERLACED
 690 } }, {
 691         .bus    = 2,
 692         .addr   = 0x41,
 693         .pixfmt = IPU_PIX_FMT_LVDS666,
 694         .detect = detect_i2c,
 695         .enable = enable_lvds,
 696         .mode   = {
 697                 .name           = "amp1024x600",
 698                 .refresh        = 60,
 699                 .xres           = 1024,
 700                 .yres           = 600,
 701                 .pixclock       = 15385,
 702                 .left_margin    = 220,
 703                 .right_margin   = 40,
 704                 .upper_margin   = 21,
 705                 .lower_margin   = 7,
 706                 .hsync_len      = 60,
 707                 .vsync_len      = 10,
 708                 .sync           = FB_SYNC_EXT,
 709                 .vmode          = FB_VMODE_NONINTERLACED
 710 } }, {
 711         .bus    = 0,
 712         .addr   = 0,
 713         .pixfmt = IPU_PIX_FMT_LVDS666,
 714         .detect = 0,
 715         .enable = enable_lvds,
 716         .mode   = {
 717                 .name           = "wvga-lvds",
 718                 .refresh        = 57,
 719                 .xres           = 800,
 720                 .yres           = 480,
 721                 .pixclock       = 15385,
 722                 .left_margin    = 220,
 723                 .right_margin   = 40,
 724                 .upper_margin   = 21,
 725                 .lower_margin   = 7,
 726                 .hsync_len      = 60,
 727                 .vsync_len      = 10,
 728                 .sync           = FB_SYNC_EXT,
 729                 .vmode          = FB_VMODE_NONINTERLACED
 730 } }, {
 731         .bus    = 2,
 732         .addr   = 0x48,
 733         .pixfmt = IPU_PIX_FMT_RGB666,
 734         .detect = detect_i2c,
 735         .enable = enable_rgb,
 736         .mode   = {
 737                 .name           = "wvga-rgb",
 738                 .refresh        = 57,
 739                 .xres           = 800,
 740                 .yres           = 480,
 741                 .pixclock       = 37037,
 742                 .left_margin    = 40,
 743                 .right_margin   = 60,
 744                 .upper_margin   = 10,
 745                 .lower_margin   = 10,
 746                 .hsync_len      = 20,
 747                 .vsync_len      = 10,
 748                 .sync           = 0,
 749                 .vmode          = FB_VMODE_NONINTERLACED
 750 } }, {
 751         .bus    = 0,
 752         .addr   = 0,
 753         .pixfmt = IPU_PIX_FMT_RGB24,
 754         .detect = NULL,
 755         .enable = enable_rgb,
 756         .mode   = {
 757                 .name           = "qvga",
 758                 .refresh        = 60,
 759                 .xres           = 320,
 760                 .yres           = 240,
 761                 .pixclock       = 37037,
 762                 .left_margin    = 38,
 763                 .right_margin   = 37,
 764                 .upper_margin   = 16,
 765                 .lower_margin   = 15,
 766                 .hsync_len      = 30,
 767                 .vsync_len      = 3,
 768                 .sync           = 0,
 769                 .vmode          = FB_VMODE_NONINTERLACED
 770 } } };
 771 size_t display_count = ARRAY_SIZE(displays);
 772
 773 int board_cfb_skip(void)
 774 {
 775         return NULL != env_get("novideo");
 776 }
 777
 778 static void setup_display(void)
 779 {
 780         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 781         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 782         int reg;
 783
 784         enable_ipu_clock();
 785         imx_setup_hdmi();
 786         /* Turn on LDB0,IPU,IPU DI0 clocks */
 787         reg = __raw_readl(&mxc_ccm->CCGR3);
 788         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 789         writel(reg, &mxc_ccm->CCGR3);
 790
 791         /* set LDB0, LDB1 clk select to 011/011 */
 792         reg = readl(&mxc_ccm->cs2cdr);
 793         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 794                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 795         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 796               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 797         writel(reg, &mxc_ccm->cs2cdr);
 798
 799         reg = readl(&mxc_ccm->cscmr2);
 800         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 801         writel(reg, &mxc_ccm->cscmr2);
 802
 803         reg = readl(&mxc_ccm->chsccdr);
 804         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 805                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 806         writel(reg, &mxc_ccm->chsccdr);
 807
 808         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 809              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 810              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 811              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 812              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 813              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 814              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 815              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 816              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 817         writel(reg, &iomux->gpr[2]);
 818
 819         reg = readl(&iomux->gpr[3]);
 820         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 821                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 822             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 823                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 824         writel(reg, &iomux->gpr[3]);
 825
 826         /* backlights off until needed */
 827         SETUP_IOMUX_PADS(backlight_pads);
 828         gpio_direction_input(LVDS_BACKLIGHT_GP);
 829         gpio_direction_input(RGB_BACKLIGHT_GP);
 830 }
 831 #endif
 832
 833 static iomux_v3_cfg_t const init_pads[] = {
 834         /* SGTL5000 sys_mclk */
 835         IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 836
 837         /* J5 - Camera MCLK */
 838         IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 839
 840         /* wl1271 pads on nitrogen6x */
 841         /* WL12XX_WL_IRQ_GP */
 842         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 843         /* WL12XX_WL_ENABLE_GP */
 844         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 845         /* WL12XX_BT_ENABLE_GP */
 846         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 847         /* USB otg power */
 848         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 849         IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 850         IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 851         IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 852         IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 853 };
 854
 855 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 856
 857 static unsigned gpios_out_low[] = {
 858         /* Disable wl1271 */
 859         IMX_GPIO_NR(6, 15),     /* disable wireless */
 860         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 861         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 862         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 863         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 864 };
 865
 866 static unsigned gpios_out_high[] = {
 867         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 868         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 869 };
 870
 871 static void set_gpios(unsigned *p, int cnt, int val)
 872 {
 873         int i;
 874
 875         for (i = 0; i < cnt; i++)
 876                 gpio_direction_output(*p++, val);
 877 }
 878
 879 int board_early_init_f(void)
 880 {
 881         setup_iomux_uart();
 882
 883         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 884         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 885         gpio_direction_input(WL12XX_WL_IRQ_GP);
 886
 887         SETUP_IOMUX_PADS(wl12xx_pads);
 888         SETUP_IOMUX_PADS(init_pads);
 889         setup_buttons();
 890
 891 #if defined(CONFIG_VIDEO_IPUV3)
 892         setup_display();
 893 #endif
 894         return 0;
 895 }
 896
 897 /*
 898  * Do not overwrite the console
 899  * Use always serial for U-Boot console
 900  */
 901 int overwrite_console(void)
 902 {
 903         return 1;
 904 }
 905
 906 int board_init(void)
 907 {
 908         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 909         struct i2c_pads_info *p = i2c_pads;
 910         int i;
 911         int stride = 1;
 912
 913 #if defined(CONFIG_MX6QDL)
 914         stride = 2;
 915         if (!is_mx6dq() && !is_mx6dqp())
 916                 p += 1;
 917 #endif
 918         clrsetbits_le32(&iomuxc_regs->gpr[1],
 919                         IOMUXC_GPR1_OTG_ID_MASK,
 920                         IOMUXC_GPR1_OTG_ID_GPIO1);
 921
 922         SETUP_IOMUX_PADS(misc_pads);
 923
 924         /* address of boot parameters */
 925         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 926
 927 #ifdef CONFIG_MXC_SPI
 928         setup_spi();
 929 #endif
 930         SETUP_IOMUX_PADS(usdhc2_pads);
 931         for (i = 0; i < I2C_BUS_CNT; i++) {
 932                 setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
 933                 p += stride;
 934         }
 935
 936 #ifdef CONFIG_SATA
 937         setup_sata();
 938 #endif
 939
 940         return 0;
 941 }
 942
 943 int checkboard(void)
 944 {
 945         int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
 946
 947         if (ret < 0) {
 948                 /* The gpios have not been probed yet. Read it myself */
 949                 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
 950                 int gpio = WL12XX_WL_IRQ_GP & 0x1f;
 951
 952                 ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 953         }
 954         if (ret)
 955                 puts("Board: Nitrogen6X\n");
 956         else
 957                 puts("Board: SABRE Lite\n");
 958
 959         return 0;
 960 }
 961
 962 struct button_key {
 963         char const      *name;
 964         unsigned        gpnum;
 965         char            ident;
 966 };
 967
 968 static struct button_key const buttons[] = {
 969         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 970         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 971         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 972         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 973         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 974         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 975 };
 976
 977 /*
 978  * generate a null-terminated string containing the buttons pressed
 979  * returns number of keys pressed
 980  */
 981 static int read_keys(char *buf)
 982 {
 983         int i, numpressed = 0;
 984         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 985                 if (!gpio_get_value(buttons[i].gpnum))
 986                         buf[numpressed++] = buttons[i].ident;
 987         }
 988         buf[numpressed] = '\0';
 989         return numpressed;
 990 }
 991
 992 static int do_kbd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 993 {
 994         char envvalue[ARRAY_SIZE(buttons)+1];
 995         int numpressed = read_keys(envvalue);
 996         env_set("keybd", envvalue);
 997         return numpressed == 0;
 998 }
 999
1000 U_BOOT_CMD(
1001         kbd, 1, 1, do_kbd,
1002         "Tests for keypresses, sets 'keybd' environment variable",
1003         "Returns 0 (true) to shell if key is pressed."
1004 );
1005
1006 #ifdef CONFIG_PREBOOT
1007 static char const kbd_magic_prefix[] = "key_magic";
1008 static char const kbd_command_prefix[] = "key_cmd";
1009
1010 static void preboot_keys(void)
1011 {
1012         int numpressed;
1013         char keypress[ARRAY_SIZE(buttons)+1];
1014         numpressed = read_keys(keypress);
1015         if (numpressed) {
1016                 char *kbd_magic_keys = env_get("magic_keys");
1017                 char *suffix;
1018                 /*
1019                  * loop over all magic keys
1020                  */
1021                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
1022                         char *keys;
1023                         char magic[sizeof(kbd_magic_prefix) + 1];
1024                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
1025                         keys = env_get(magic);
1026                         if (keys) {
1027                                 if (!strcmp(keys, keypress))
1028                                         break;
1029                         }
1030                 }
1031                 if (*suffix) {
1032                         char cmd_name[sizeof(kbd_command_prefix) + 1];
1033                         char *cmd;
1034                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
1035                         cmd = env_get(cmd_name);
1036                         if (cmd) {
1037                                 env_set("preboot", cmd);
1038                                 return;
1039                         }
1040                 }
1041         }
1042 }
1043 #endif
1044
1045 #ifdef CONFIG_CMD_BMODE
1046 static const struct boot_mode board_boot_modes[] = {
1047         /* 4 bit bus width */
1048         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1049         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1050         {NULL,          0},
1051 };
1052 #endif
1053
1054 int misc_init_r(void)
1055 {
1056         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
1057         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
1058         gpio_request(GP_USB_OTG_PWR, "usbotg power");
1059         gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
1060         gpio_request(IMX_GPIO_NR(2, 2), "back");
1061         gpio_request(IMX_GPIO_NR(2, 4), "home");
1062         gpio_request(IMX_GPIO_NR(2, 1), "menu");
1063         gpio_request(IMX_GPIO_NR(2, 3), "search");
1064         gpio_request(IMX_GPIO_NR(7, 13), "volup");
1065         gpio_request(IMX_GPIO_NR(4, 5), "voldown");
1066 #ifdef CONFIG_PREBOOT
1067         preboot_keys();
1068 #endif
1069
1070 #ifdef CONFIG_CMD_BMODE
1071         add_board_boot_modes(board_boot_modes);
1072 #endif
1073         env_set_hex("reset_cause", get_imx_reset_cause());
1074         return 0;
1075 }