board/bluewater/snapper9260/snapper9260.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Bluewater Systems Snapper 9260/9G20 modules
   4  *
   5  * (C) Copyright 2011 Bluewater Systems
   6  *   Author: Andre Renaud <andre@bluewatersys.com>
   7  *   Author: Ryan Mallon <ryan@bluewatersys.com>
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <init.h>
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-types.h>
  16 #include <asm/arch/at91sam9260_matrix.h>
  17 #include <asm/arch/at91sam9_smc.h>
  18 #include <asm/arch/at91_common.h>
  19 #include <asm/arch/clk.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/atmel_serial.h>
  22 #include <net.h>
  23 #include <netdev.h>
  24 #include <i2c.h>
  25 #include <pca953x.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* IO Expander pins */
  30 #define IO_EXP_ETH_RESET        (0 << 1)
  31 #define IO_EXP_ETH_POWER        (1 << 1)
  32
  33 static void macb_hw_init(void)
  34 {
  35         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  36
  37         at91_periph_clk_enable(ATMEL_ID_EMAC0);
  38
  39         /* Disable pull-ups to prevent PHY going into test mode */
  40         writel(pin_to_mask(AT91_PIN_PA14) |
  41                pin_to_mask(AT91_PIN_PA15) |
  42                pin_to_mask(AT91_PIN_PA18),
  43                &pioa->pudr);
  44
  45         /* Power down ethernet */
  46         pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
  47         pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
  48
  49         /* Hold ethernet in reset */
  50         pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
  51         pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
  52
  53         /* Enable ethernet power */
  54         pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
  55
  56         at91_phy_reset();
  57
  58         /* Bring the ethernet out of reset */
  59         pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
  60
  61         /* The phy internal reset take 21ms */
  62         udelay(21 * 1000);
  63
  64         /* Re-enable pull-up */
  65         writel(pin_to_mask(AT91_PIN_PA14) |
  66                pin_to_mask(AT91_PIN_PA15) |
  67                pin_to_mask(AT91_PIN_PA18),
  68                &pioa->puer);
  69
  70         at91_macb_hw_init();
  71 }
  72
  73 static void nand_hw_init(void)
  74 {
  75         struct at91_smc *smc       = (struct at91_smc    *)ATMEL_BASE_SMC;
  76         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  77         unsigned long csa;
  78
  79         /* Enable CS3 as NAND/SmartMedia */
  80         csa = readl(&matrix->ebicsa);
  81         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  82         writel(csa, &matrix->ebicsa);
  83
  84         /* Configure SMC CS3 for NAND/SmartMedia */
  85         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  86                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  87                &smc->cs[3].setup);
  88         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
  89                AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  90                &smc->cs[3].pulse);
  91         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  92                &smc->cs[3].cycle);
  93         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  94                AT91_SMC_MODE_EXNW_DISABLE |
  95                AT91_SMC_MODE_DBW_8 |
  96                AT91_SMC_MODE_TDF_CYCLE(3),
  97                &smc->cs[3].mode);
  98
  99         /* Configure RDY/BSY */
 100         gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
 101         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 102
 103         /* Enable NandFlash */
 104         gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
 105         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 106 }
 107
 108 int board_init(void)
 109 {
 110         at91_periph_clk_enable(ATMEL_ID_PIOA);
 111         at91_periph_clk_enable(ATMEL_ID_PIOB);
 112         at91_periph_clk_enable(ATMEL_ID_PIOC);
 113
 114         /* The mach-type is the same for both Snapper 9260 and 9G20 */
 115         gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
 116
 117         /* Address of boot parameters */
 118         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 119
 120         /* Initialise peripherals */
 121         at91_seriald_hw_init();
 122         i2c_set_bus_num(0);
 123         nand_hw_init();
 124         macb_hw_init();
 125
 126         return 0;
 127 }
 128
 129 int board_eth_init(bd_t *bis)
 130 {
 131         return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
 132 }
 133
 134 int dram_init(void)
 135 {
 136         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 137                                     CONFIG_SYS_SDRAM_SIZE);
 138         return 0;
 139 }
 140
 141 void reset_phy(void)
 142 {
 143 }
 144
 145 static struct atmel_serial_platdata at91sam9260_serial_plat = {
 146         .base_addr = ATMEL_BASE_DBGU,
 147 };
 148
 149 U_BOOT_DEVICE(at91sam9260_serial) = {
 150         .name   = "serial_atmel",
 151         .platdata = &at91sam9260_serial_plat,
 152 };