board/birdland/bav335x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Birdland Audio BAV335x Network Processor
   6  *
   7  * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <errno.h>
  13 #include <init.h>
  14 #include <serial.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mem.h>
  25 #include <asm/io.h>
  26 #include <asm/emif.h>
  27 #include <asm/gpio.h>
  28 #include <i2c.h>
  29 #include <miiphy.h>
  30 #include <cpsw.h>
  31 #include <power/tps65217.h>
  32 #include <power/tps65910.h>
  33 #include <env_internal.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 /* GPIO that controls power to DDR on EVM-SK */
  40 #define GPIO_DDR_VTT_EN         7
  41
  42 static __maybe_unused struct ctrl_dev *cdev =
  43                 (struct ctrl_dev *)CTRL_DEVICE_BASE;
  44
  45
  46
  47 /*
  48  * Read header information from EEPROM into global structure.
  49  */
  50 static int read_eeprom(struct board_eeconfig *header)
  51 {
  52         /* Check if baseboard eeprom is available */
  53         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
  54                 return -ENODEV;
  55
  56         /* read the eeprom using i2c */
  57         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  58                      sizeof(struct board_eeconfig)))
  59                 return -EIO;
  60
  61         if (header->magic != BOARD_MAGIC) {
  62                 /* read the i2c eeprom again using only a 1 byte address */
  63                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  64                              sizeof(struct board_eeconfig)))
  65                         return -EIO;
  66
  67                 if (header->magic != BOARD_MAGIC)
  68                         return -EINVAL;
  69         }
  70         return 0;
  71 }
  72
  73
  74
  75
  76 enum board_type get_board_type(bool debug)
  77 {
  78         int ecode;
  79         struct board_eeconfig header;
  80
  81         ecode = read_eeprom(&header);
  82         if (ecode == 0) {
  83                 if (header.version[1] == 'A') {
  84                         if (debug)
  85                                 puts("=== Detected Board model BAV335x Rev.A");
  86                         return BAV335A;
  87                 } else if (header.version[1] == 'B') {
  88                         if (debug)
  89                                 puts("=== Detected Board model BAV335x Rev.B");
  90                         return BAV335B;
  91                 } else if (debug) {
  92                         puts("### Un-known board model in serial-EE\n");
  93                 }
  94         } else if (debug) {
  95                 switch (ecode) {
  96                 case -ENODEV:
  97                         puts("### Board doesn't have a serial-EE\n");
  98                         break;
  99                 case -EINVAL:
 100                         puts("### Board serial-EE signature is incorrect.\n");
 101                         break;
 102                 default:
 103                         puts("### IO Error reading serial-EE.\n");
 104                         break;
 105                 }
 106         }
 107
 108 #if (CONFIG_BAV_VERSION == 1)
 109         if (debug)
 110                 puts("### Selecting BAV335A as per config\n");
 111         return BAV335A;
 112 #elif (CONFIG_BAV_VERSION == 2)
 113         if (debug)
 114                 puts("### Selecting BAV335B as per config\n");
 115         return BAV335B;
 116 #endif
 117 #if (NOT_DEFINED == 2)
 118 #error "SHOULD NEVER DISPLAY THIS"
 119 #endif
 120
 121         if (debug)
 122                 puts("### Defaulting to model BAV335x Rev.B\n");
 123         return BAV335B;
 124 }
 125
 126
 127
 128 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 129 static const struct ddr_data ddr3_bav335x_data = {
 130         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 131         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 132         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 133         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 134 };
 135
 136 static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
 137         .cmd0csratio = MT41K256M16HA125E_RATIO,
 138         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 139         .cmd1csratio = MT41K256M16HA125E_RATIO,
 140         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 141         .cmd2csratio = MT41K256M16HA125E_RATIO,
 142         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 143 };
 144
 145
 146 static struct emif_regs ddr3_bav335x_emif_reg_data = {
 147         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 148         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 149         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 150         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 151         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 152         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 153         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 154 };
 155
 156
 157 #ifdef CONFIG_SPL_OS_BOOT
 158 int spl_start_uboot(void)
 159 {
 160         /* break into full u-boot on 'c' */
 161         if (serial_tstc() && serial_getc() == 'c')
 162                 return 1;
 163
 164 #ifdef CONFIG_SPL_ENV_SUPPORT
 165         env_init();
 166         env_load();
 167         if (env_get_yesno("boot_os") != 1)
 168                 return 1;
 169 #endif
 170
 171         return 0;
 172 }
 173 #endif
 174
 175 #define OSC     (V_OSCK/1000000)
 176 const struct dpll_params dpll_ddr = {
 177                 266, OSC-1, 1, -1, -1, -1, -1};
 178 const struct dpll_params dpll_ddr_evm_sk = {
 179                 303, OSC-1, 1, -1, -1, -1, -1};
 180 const struct dpll_params dpll_ddr_bone_black = {
 181                 400, OSC-1, 1, -1, -1, -1, -1};
 182
 183 void am33xx_spl_board_init(void)
 184 {
 185         /* debug print detect status */
 186         (void)get_board_type(true);
 187
 188         /* Get the frequency */
 189         /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
 190         dpll_mpu_opp100.m = MPUPLL_M_1000;
 191
 192         if (i2c_probe(TPS65217_CHIP_PM))
 193                 return;
 194
 195         /* Set the USB Current Limit */
 196         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
 197                                TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
 198                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 199                 puts("! tps65217_reg_write: could not set USB limit\n");
 200
 201         /* Set the Core Voltage (DCDC3) to 1.125V */
 202         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 203                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 204                 puts("! tps65217_reg_write: could not set Core Voltage\n");
 205                 return;
 206         }
 207
 208         /* Set CORE Frequencies to OPP100 */
 209         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 210
 211         /* Set the MPU Voltage (DCDC2) */
 212         if (tps65217_voltage_update(TPS65217_DEFDCDC2,
 213                                     TPS65217_DCDC_VOLT_SEL_1325MV)) {
 214                 puts("! tps65217_reg_write: could not set MPU Voltage\n");
 215                 return;
 216         }
 217
 218         /*
 219          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 220          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 221          */
 222         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
 223                                TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
 224                 puts("! tps65217_reg_write: could not set LDO3\n");
 225
 226         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
 227                                TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
 228                 puts("! tps65217_reg_write: could not set LDO4\n");
 229
 230         /* Set MPU Frequency to what we detected now that voltages are set */
 231         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 232 }
 233
 234 const struct dpll_params *get_dpll_ddr_params(void)
 235 {
 236         enable_i2c0_pin_mux();
 237         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 238
 239         return &dpll_ddr_bone_black;
 240 }
 241
 242 void set_uart_mux_conf(void)
 243 {
 244 #if CONFIG_CONS_INDEX == 1
 245         enable_uart0_pin_mux();
 246 #elif CONFIG_CONS_INDEX == 2
 247         enable_uart1_pin_mux();
 248 #elif CONFIG_CONS_INDEX == 3
 249         enable_uart2_pin_mux();
 250 #elif CONFIG_CONS_INDEX == 4
 251         enable_uart3_pin_mux();
 252 #elif CONFIG_CONS_INDEX == 5
 253         enable_uart4_pin_mux();
 254 #elif CONFIG_CONS_INDEX == 6
 255         enable_uart5_pin_mux();
 256 #endif
 257 }
 258
 259 void set_mux_conf_regs(void)
 260 {
 261         enum board_type board;
 262
 263         board = get_board_type(false);
 264         enable_board_pin_mux(board);
 265 }
 266
 267 const struct ctrl_ioregs ioregs_bonelt = {
 268         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 269         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 270         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 271         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 272         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 273 };
 274
 275
 276 void sdram_init(void)
 277 {
 278         config_ddr(400, &ioregs_bonelt,
 279                    &ddr3_bav335x_data,
 280                    &ddr3_bav335x_cmd_ctrl_data,
 281                    &ddr3_bav335x_emif_reg_data, 0);
 282 }
 283 #endif
 284
 285 /*
 286  * Basic board specific setup.  Pinmux has been handled already.
 287  */
 288 int board_init(void)
 289 {
 290 #if defined(CONFIG_HW_WATCHDOG)
 291         hw_watchdog_init();
 292 #endif
 293
 294         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 295 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 296         gpmc_init();
 297 #endif
 298         return 0;
 299 }
 300
 301 #ifdef CONFIG_BOARD_LATE_INIT
 302 int board_late_init(void)
 303 {
 304 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 305         env_set("board_name", "BAV335xB");
 306         env_set("board_rev", "B"); /* Fix me, but why bother.. */
 307 #endif
 308         return 0;
 309 }
 310 #endif
 311
 312
 313 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 314         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 315 static void cpsw_control(int enabled)
 316 {
 317         /* VTP can be added here */
 318         return;
 319 }
 320
 321 static struct cpsw_slave_data cpsw_slaves[] = {
 322         {
 323                 .slave_reg_ofs  = 0x208,
 324                 .sliver_reg_ofs = 0xd80,
 325                 .phy_addr       = 0,
 326         },
 327         {
 328                 .slave_reg_ofs  = 0x308,
 329                 .sliver_reg_ofs = 0xdc0,
 330                 .phy_addr       = 1,
 331         },
 332 };
 333
 334 static struct cpsw_platform_data cpsw_data = {
 335         .mdio_base              = CPSW_MDIO_BASE,
 336         .cpsw_base              = CPSW_BASE,
 337         .mdio_div               = 0xff,
 338         .channels               = 8,
 339         .cpdma_reg_ofs  = 0x800,
 340         .slaves                 = 1,
 341         .slave_data             = cpsw_slaves,
 342         .ale_reg_ofs    = 0xd00,
 343         .ale_entries    = 1024,
 344         .host_port_reg_ofs      = 0x108,
 345         .hw_stats_reg_ofs       = 0x900,
 346         .bd_ram_ofs             = 0x2000,
 347         .mac_control    = (1 << 5),
 348         .control                = cpsw_control,
 349         .host_port_num  = 0,
 350         .version                = CPSW_CTRL_VERSION_2,
 351 };
 352 #endif
 353
 354
 355 /*
 356  * This function will:
 357  * Perform fixups to the PHY present on certain boards.  We only need this
 358  * function in:
 359  * - SPL with either CPSW or USB ethernet support
 360  * - Full U-Boot, with either CPSW or USB ethernet
 361  * Build in only these cases to avoid warnings about unused variables
 362  * when we build an SPL that has neither option but full U-Boot will.
 363  */
 364 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
 365                 defined(CONFIG_SPL_BUILD)) || \
 366         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 367           defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
 368          !defined(CONFIG_SPL_BUILD))
 369 int board_eth_init(bd_t *bis)
 370 {
 371         int ecode, rv, n;
 372         uint8_t mac_addr[6];
 373         struct board_eeconfig header;
 374         __maybe_unused enum board_type board;
 375
 376         /* Default manufacturing address; used when no EE or invalid */
 377         n = 0;
 378         mac_addr[0] = 0;
 379         mac_addr[1] = 0x20;
 380         mac_addr[2] = 0x18;
 381         mac_addr[3] = 0x1C;
 382         mac_addr[4] = 0x00;
 383         mac_addr[5] = 0x01;
 384
 385         ecode = read_eeprom(&header);
 386         /* if we have a valid EE, get mac address from there */
 387         if ((ecode == 0) &&
 388             is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
 389                 memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
 390         }
 391
 392
 393 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 394         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 395
 396         if (!env_get("ethaddr")) {
 397                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 398
 399                 if (is_valid_ethaddr(mac_addr))
 400                         eth_env_set_enetaddr("ethaddr", mac_addr);
 401         }
 402
 403 #ifdef CONFIG_DRIVER_TI_CPSW
 404
 405         board = get_board_type(false);
 406
 407         /* Rev.A uses 10/100 PHY in mii mode */
 408         if (board == BAV335A) {
 409                 writel(MII_MODE_ENABLE, &cdev->miisel);
 410                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
 411                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
 412         }
 413         /* Rev.B (default) uses GB PHY in rmii mode */
 414         else {
 415                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 416                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
 417                                 = PHY_INTERFACE_MODE_RGMII;
 418         }
 419
 420         rv = cpsw_register(&cpsw_data);
 421         if (rv < 0)
 422                 printf("Error %d registering CPSW switch\n", rv);
 423         else
 424                 n += rv;
 425 #endif
 426
 427 #endif
 428
 429         return n;
 430 }
 431 #endif