board/atmel/sama5d2_xplained/sama5d2_xplained.c

   1 /*
   2  * Copyright (C) 2015 Atmel Corporation
   3  *                    Wenyou.Yang <wenyou.yang@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <atmel_hlcdc.h>
  10 #include <debug_uart.h>
  11 #include <lcd.h>
  12 #include <version.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/at91_common.h>
  15 #include <asm/arch/atmel_pio4.h>
  16 #include <asm/arch/atmel_mpddrc.h>
  17 #include <asm/arch/atmel_sdhci.h>
  18 #include <asm/arch/clk.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/sama5d2.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static void board_usb_hw_init(void)
  25 {
  26         atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
  27 }
  28
  29 #ifdef CONFIG_LCD
  30 vidinfo_t panel_info = {
  31         .vl_col = 480,
  32         .vl_row = 272,
  33         .vl_clk = 9000000,
  34         .vl_bpix = LCD_BPP,
  35         .vl_tft = 1,
  36         .vl_hsync_len = 41,
  37         .vl_left_margin = 2,
  38         .vl_right_margin = 2,
  39         .vl_vsync_len = 11,
  40         .vl_upper_margin = 2,
  41         .vl_lower_margin = 2,
  42         .mmio = ATMEL_BASE_LCDC,
  43 };
  44
  45 /* No power up/down pin for the LCD pannel */
  46 void lcd_enable(void)   { /* Empty! */ }
  47 void lcd_disable(void)  { /* Empty! */ }
  48
  49 unsigned int has_lcdc(void)
  50 {
  51         return 1;
  52 }
  53
  54 static void board_lcd_hw_init(void)
  55 {
  56         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
  57         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
  58         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
  59         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
  60         atmel_pio4_set_a_periph(AT91_PIO_PORTD,  0, 0); /* LCDPCK */
  61         atmel_pio4_set_a_periph(AT91_PIO_PORTD,  1, 0); /* LCDDEN */
  62
  63         /* LCDDAT0 */
  64         /* LCDDAT1 */
  65         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
  66         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
  67         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
  68         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
  69         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
  70         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
  71
  72         /* LCDDAT8 */
  73         /* LCDDAT9 */
  74         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
  75         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
  76         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
  77         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
  78         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
  79         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
  80
  81         /* LCDD16 */
  82         /* LCDD17 */
  83         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
  84         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
  85         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
  86         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
  87         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
  88         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
  89
  90         at91_periph_clk_enable(ATMEL_ID_LCDC);
  91 }
  92
  93 #ifdef CONFIG_LCD_INFO
  94 void lcd_show_board_info(void)
  95 {
  96         ulong dram_size;
  97         int i;
  98         char temp[32];
  99
 100         lcd_printf("%s\n", U_BOOT_VERSION);
 101         lcd_printf("2015 ATMEL Corp\n");
 102         lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 103                    strmhz(temp, get_cpu_clk_rate()));
 104
 105         dram_size = 0;
 106         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 107                 dram_size += gd->bd->bi_dram[i].size;
 108
 109         lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
 110 }
 111 #endif /* CONFIG_LCD_INFO */
 112 #endif /* CONFIG_LCD */
 113
 114 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 115 static void board_uart1_hw_init(void)
 116 {
 117         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1);  /* URXD1 */
 118         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);  /* UTXD1 */
 119
 120         at91_periph_clk_enable(ATMEL_ID_UART1);
 121 }
 122
 123 void board_debug_uart_init(void)
 124 {
 125         board_uart1_hw_init();
 126 }
 127 #endif
 128
 129 #ifdef CONFIG_BOARD_EARLY_INIT_F
 130 int board_early_init_f(void)
 131 {
 132 #ifdef CONFIG_DEBUG_UART
 133         debug_uart_init();
 134 #endif
 135
 136         return 0;
 137 }
 138 #endif
 139
 140 int board_init(void)
 141 {
 142         /* address of boot parameters */
 143         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 144
 145 #ifdef CONFIG_LCD
 146         board_lcd_hw_init();
 147 #endif
 148 #ifdef CONFIG_CMD_USB
 149         board_usb_hw_init();
 150 #endif
 151
 152         return 0;
 153 }
 154
 155 int dram_init(void)
 156 {
 157         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 158                                     CONFIG_SYS_SDRAM_SIZE);
 159         return 0;
 160 }
 161
 162 #define AT24MAC_MAC_OFFSET      0x9a
 163
 164 #ifdef CONFIG_MISC_INIT_R
 165 int misc_init_r(void)
 166 {
 167 #ifdef CONFIG_I2C_EEPROM
 168         at91_set_ethaddr(AT24MAC_MAC_OFFSET);
 169 #endif
 170
 171         return 0;
 172 }
 173 #endif
 174
 175 /* SPL */
 176 #ifdef CONFIG_SPL_BUILD
 177 void spl_board_init(void)
 178 {
 179 }
 180
 181 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
 182 {
 183         ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
 184
 185         ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 186                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 187                     ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
 188                     ATMEL_MPDDRC_CR_DIC_DS |
 189                     ATMEL_MPDDRC_CR_DIS_DLL |
 190                     ATMEL_MPDDRC_CR_NB_8BANKS |
 191                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 192                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 193
 194         ddrc->rtr = 0x511;
 195
 196         ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 197                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 198                       4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 199                       9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 200                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 201                       4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 202                       4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 203                       4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 204
 205         ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
 206                       29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 207                       0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 208                       3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
 209
 210         ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
 211                       0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 212                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 213                       4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 214                       7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
 215 }
 216
 217 void mem_init(void)
 218 {
 219         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 220         struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 221         struct atmel_mpddrc_config ddrc_config;
 222         u32 reg;
 223
 224         ddrc_conf(&ddrc_config);
 225
 226         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 227         writel(AT91_PMC_DDR, &pmc->scer);
 228
 229         reg = readl(&mpddrc->io_calibr);
 230         reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
 231         reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
 232         reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
 233         reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
 234         writel(reg, &mpddrc->io_calibr);
 235
 236         writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
 237                &mpddrc->rd_data_path);
 238
 239         ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
 240
 241         writel(0x3, &mpddrc->cal_mr4);
 242         writel(64, &mpddrc->tim_cal);
 243 }
 244
 245 void at91_pmc_init(void)
 246 {
 247         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 248         u32 tmp;
 249
 250         /*
 251          * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
 252          * so we need to slow down and configure MCKR accordingly.
 253          * This is why we have a special flavor of the switching function.
 254          */
 255         tmp = AT91_PMC_MCKR_PLLADIV_2 |
 256               AT91_PMC_MCKR_MDIV_3 |
 257               AT91_PMC_MCKR_CSS_MAIN;
 258         at91_mck_init_down(tmp);
 259
 260         tmp = AT91_PMC_PLLAR_29 |
 261               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 262               AT91_PMC_PLLXR_MUL(82) |
 263               AT91_PMC_PLLXR_DIV(1);
 264         at91_plla_init(tmp);
 265
 266         writel(0x0 << 8, &pmc->pllicpr);
 267
 268         tmp = AT91_PMC_MCKR_H32MXDIV |
 269               AT91_PMC_MCKR_PLLADIV_2 |
 270               AT91_PMC_MCKR_MDIV_3 |
 271               AT91_PMC_MCKR_CSS_PLLA;
 272         at91_mck_init(tmp);
 273 }
 274 #endif