1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
5 * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
10 #include <asm/arch/at91sam9_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/at91_sfr.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/gpio.h>
16 #include <debug_uart.h>
17 #include <asm/mach-types.h>
19 extern void at91_pda_detect(void);
21 DECLARE_GLOBAL_DATA_PTR;
23 void at91_prepare_cpu_var(void);
25 #ifdef CONFIG_CMD_NAND
26 static void sam9x60ek_nand_hw_init(void)
28 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
29 struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
32 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
33 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
34 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
35 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
36 /* Enable NandFlash */
37 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
38 /* Configure RDY/BSY */
39 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
40 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
41 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
42 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
43 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
44 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
45 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
46 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
47 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
49 at91_periph_clk_enable(ATMEL_ID_PIOD);
52 csa = readl(&sfr->ebicsa);
53 csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
55 /* Configure IO drive */
56 csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
58 writel(csa, &sfr->ebicsa);
60 /* Configure SMC CS3 for NAND/SmartMedia */
61 writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
63 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
64 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
67 writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
70 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
71 #ifdef CONFIG_SYS_NAND_DBW_16
72 AT91_SMC_MODE_DBW_16 |
73 #else /* CONFIG_SYS_NAND_DBW_8 */
76 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
81 #ifdef CONFIG_BOARD_LATE_INIT
82 int board_late_init(void)
84 at91_prepare_cpu_var();
92 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
93 void board_debug_uart_init(void)
95 at91_seriald_hw_init();
99 #ifdef CONFIG_BOARD_EARLY_INIT_F
100 int board_early_init_f(void)
102 #ifdef CONFIG_DEBUG_UART
111 /* address of boot parameters */
112 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
114 #ifdef CONFIG_CMD_NAND
115 sam9x60ek_nand_hw_init();
122 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
123 CONFIG_SYS_SDRAM_SIZE);