board/atmel/at91sam9261ek/at91sam9261ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <init.h>
  11 #include <vsprintf.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/at91sam9261.h>
  14 #include <asm/arch/at91sam9261_matrix.h>
  15 #include <asm/arch/at91sam9_smc.h>
  16 #include <asm/arch/at91_common.h>
  17 #include <asm/arch/at91_rstc.h>
  18 #include <asm/arch/clk.h>
  19 #include <asm/arch/gpio.h>
  20 #include <lcd.h>
  21 #include <atmel_lcdc.h>
  22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  23 #include <net.h>
  24 #include <netdev.h>
  25 #endif
  26 #include <asm/mach-types.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34
  35 #ifdef CONFIG_CMD_NAND
  36 static void at91sam9261ek_nand_hw_init(void)
  37 {
  38         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  39         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  40         unsigned long csa;
  41
  42         /* Enable CS3 */
  43         csa = readl(&matrix->ebicsa);
  44         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  45
  46         writel(csa, &matrix->ebicsa);
  47
  48         /* Configure SMC CS3 for NAND/SmartMedia */
  49 #ifdef CONFIG_AT91SAM9G10EK
  50         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  51                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  52                 &smc->cs[3].setup);
  53         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
  54                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
  55                 &smc->cs[3].pulse);
  56         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  57                 &smc->cs[3].cycle);
  58 #else
  59         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  60                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  61                 &smc->cs[3].setup);
  62         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  63                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  64                 &smc->cs[3].pulse);
  65         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  66                 &smc->cs[3].cycle);
  67 #endif
  68         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  69                        AT91_SMC_MODE_EXNW_DISABLE |
  70 #ifdef CONFIG_SYS_NAND_DBW_16
  71                        AT91_SMC_MODE_DBW_16 |
  72 #else /* CONFIG_SYS_NAND_DBW_8 */
  73                        AT91_SMC_MODE_DBW_8 |
  74 #endif
  75                        AT91_SMC_MODE_TDF_CYCLE(2),
  76                        &smc->cs[3].mode);
  77
  78         at91_periph_clk_enable(ATMEL_ID_PIOC);
  79
  80         /* Configure RDY/BSY */
  81         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  82
  83         /* Enable NandFlash */
  84         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  85
  86         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
  87         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
  88 }
  89 #endif
  90
  91 #ifdef CONFIG_DRIVER_DM9000
  92 static void at91sam9261ek_dm9000_hw_init(void)
  93 {
  94         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  95
  96         /* Configure SMC CS2 for DM9000 */
  97 #ifdef CONFIG_AT91SAM9G10EK
  98         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
  99                 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
 100                 &smc->cs[2].setup);
 101         writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
 102                 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
 103                 &smc->cs[2].pulse);
 104         writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
 105                 &smc->cs[2].cycle);
 106         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 107                        AT91_SMC_MODE_EXNW_DISABLE |
 108                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 109                        AT91_SMC_MODE_TDF_CYCLE(1),
 110                        &smc->cs[2].mode);
 111 #else
 112         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
 113                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
 114                 &smc->cs[2].setup);
 115         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
 116                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
 117                 &smc->cs[2].pulse);
 118         writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
 119                 &smc->cs[2].cycle);
 120         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 121                        AT91_SMC_MODE_EXNW_DISABLE |
 122                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 123                        AT91_SMC_MODE_TDF_CYCLE(1),
 124                        &smc->cs[2].mode);
 125 #endif
 126
 127         /* Configure Reset signal as output */
 128         at91_set_gpio_output(AT91_PIN_PC10, 0);
 129
 130         /* Configure Interrupt pin as input, no pull-up */
 131         at91_set_gpio_input(AT91_PIN_PC11, 0);
 132 }
 133 #endif
 134
 135 #ifdef CONFIG_LCD
 136 vidinfo_t panel_info = {
 137         .vl_col =               240,
 138         .vl_row =               320,
 139         .vl_clk =               4965000,
 140         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
 141                                 ATMEL_LCDC_INVFRAME_INVERTED,
 142         .vl_bpix =              3,
 143         .vl_tft =               1,
 144         .vl_hsync_len =         5,
 145         .vl_left_margin =       1,
 146         .vl_right_margin =      33,
 147         .vl_vsync_len =         1,
 148         .vl_upper_margin =      1,
 149         .vl_lower_margin =      0,
 150         .mmio =                 ATMEL_BASE_LCDC,
 151 };
 152
 153 void lcd_enable(void)
 154 {
 155         at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
 156 }
 157
 158 void lcd_disable(void)
 159 {
 160         at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
 161 }
 162
 163 static void at91sam9261ek_lcd_hw_init(void)
 164 {
 165         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
 166         at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
 167         at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
 168         at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
 169         at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
 170         at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
 171         at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
 172         at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
 173         at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
 174         at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
 175         at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
 176         at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
 177         at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
 178         at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
 179         at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
 180         at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
 181         at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
 182         at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
 183         at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
 184         at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
 185         at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
 186         at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
 187
 188         at91_system_clk_enable(AT91_PMC_HCK1);
 189
 190         /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
 191 #ifdef CONFIG_AT91SAM9261EK
 192         gd->fb_base = ATMEL_BASE_SRAM;
 193 #endif
 194 }
 195
 196 #ifdef CONFIG_LCD_INFO
 197 #include <nand.h>
 198 #include <version.h>
 199
 200 void lcd_show_board_info(void)
 201 {
 202         ulong dram_size, nand_size;
 203         int i;
 204         char temp[32];
 205
 206         lcd_printf ("%s\n", U_BOOT_VERSION);
 207         lcd_printf ("(C) 2008 ATMEL Corp\n");
 208         lcd_printf ("at91support@atmel.com\n");
 209         lcd_printf ("%s CPU at %s MHz\n",
 210                 ATMEL_CPU_NAME,
 211                 strmhz(temp, get_cpu_clk_rate()));
 212
 213         dram_size = 0;
 214         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 215                 dram_size += gd->bd->bi_dram[i].size;
 216         nand_size = 0;
 217         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 218                 nand_size += get_nand_dev_by_index(i)->size;
 219         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 220                 dram_size >> 20,
 221                 nand_size >> 20 );
 222 }
 223 #endif /* CONFIG_LCD_INFO */
 224 #endif
 225
 226 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 227 void board_debug_uart_init(void)
 228 {
 229         at91_seriald_hw_init();
 230 }
 231 #endif
 232
 233 #ifdef CONFIG_BOARD_EARLY_INIT_F
 234 int board_early_init_f(void)
 235 {
 236 #ifdef CONFIG_DEBUG_UART
 237         debug_uart_init();
 238 #endif
 239         return 0;
 240 }
 241 #endif
 242
 243 int board_init(void)
 244 {
 245 #ifdef CONFIG_AT91SAM9G10EK
 246         /* arch number of AT91SAM9G10EK-Board */
 247         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
 248 #else
 249         /* arch number of AT91SAM9261EK-Board */
 250         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 251 #endif
 252         /* adress of boot parameters */
 253         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 254
 255 #ifdef CONFIG_CMD_NAND
 256         at91sam9261ek_nand_hw_init();
 257 #endif
 258 #ifdef CONFIG_DRIVER_DM9000
 259         at91sam9261ek_dm9000_hw_init();
 260 #endif
 261 #ifdef CONFIG_LCD
 262         at91sam9261ek_lcd_hw_init();
 263 #endif
 264         return 0;
 265 }
 266
 267 #ifdef CONFIG_DRIVER_DM9000
 268 int board_eth_init(bd_t *bis)
 269 {
 270         return dm9000_initialize(bis);
 271 }
 272 #endif
 273
 274 int dram_init(void)
 275 {
 276         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 277                 CONFIG_SYS_SDRAM_SIZE);
 278
 279         return 0;
 280 }
 281
 282 #ifdef CONFIG_RESET_PHY_R
 283 void reset_phy(void)
 284 {
 285 #ifdef CONFIG_DRIVER_DM9000
 286         /*
 287          * Initialize ethernet HW addr prior to starting Linux,
 288          * needed for nfsroot
 289          */
 290         eth_init();
 291 #endif
 292 }
 293 #endif