1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
13 #include <asm/m5329.h>
14 #include <asm/immap_5329.h>
17 /* needed for astro bus: */
21 DECLARE_GLOBAL_DATA_PTR;
22 extern void uart_port_conf(void);
27 puts("ASTRO MCF5373L (Urmel) Board\n");
33 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
34 sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
37 * GPIO configuration for bus should be set correctly from reset,
38 * so we do not care! First, set up address space: at this point,
39 * we should be running from internal SRAM;
40 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
41 * and do not care where it is
43 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
45 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
48 * I am not sure from the data sheet, but it seems burst length
49 * has to be 8 for the 16 bit data bus we use;
50 * so these values are for BL = 8
52 __raw_writel(0x33211530, &sdp->cfg1);
53 __raw_writel(0x56570000, &sdp->cfg2);
54 /* send PrechargeALL, REF and IREF remain cleared! */
55 __raw_writel(0xE1462C02, &sdp->ctrl);
57 /* refresh SDRAM twice */
58 __raw_writel(0xE1462C04, &sdp->ctrl);
60 __raw_writel(0xE1462C04, &sdp->ctrl);
62 __raw_writel(0x008D0000, &sdp->mode);
64 __raw_writel(0x80010000, &sdp->mode);
65 /* wait until DLL is locked */
68 * enable automatic refresh, lock mode register,
69 * clear iref and ipall
71 __raw_writel(0x71462C00, &sdp->ctrl);
72 /* Dummy write to start SDRAM */
73 writel(0, CONFIG_SYS_SDRAM_BASE);
77 * for get_ram_size() to work, both CS areas have to be
78 * configured, i.e. CS1 has to be explicitely disabled, else
79 * probing for memory will cause the SDRAM bus to hang!
80 * (Do not rely on the SDCS register(s) being set to 0x00000000
81 * during reset as stated in the data sheet.)
83 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
84 0x80000000 - CONFIG_SYS_SDRAM_BASE);
89 #define UART_BASE MMAP_UART0
90 int rs_serial_init(int port, int baud)
97 uart = (uart_t *)(MMAP_UART0);
100 uart = (uart_t *)(MMAP_UART1);
103 uart = (uart_t *)(MMAP_UART2);
106 uart = (uart_t *)(MMAP_UART0);
111 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
112 writeb(UART_UCR_RESET_RX, &uart->ucr);
113 writeb(UART_UCR_RESET_TX, &uart->ucr);
114 writeb(UART_UCR_RESET_ERROR, &uart->ucr);
115 writeb(UART_UCR_RESET_MR, &uart->ucr);
118 writeb(0, &uart->uimr);
120 /* write to CSR: RX/TX baud rate from timers */
121 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
123 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
124 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
126 /* Setting up BaudRate */
127 counter = (u32) (gd->bus_clk / (baud));
130 /* write to CTUR: divide counter upper byte */
131 writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
132 /* write to CTLR: divide counter lower byte */
133 writeb((u8) (counter & 0x00ff), &uart->ubg2);
135 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
140 void astro_put_char(char ch)
145 uart = (uart_t *)(MMAP_UART0);
147 * Wait for last character to go. Timeout of 6ms should
148 * be enough for our lowest baud rate of 2400.
150 timer = get_timer(0);
151 while (get_timer(timer) < 6) {
152 if (readb(&uart->usr) & UART_USR_TXRDY)
155 writeb(ch, &uart->utb);
160 int astro_is_char(void)
164 uart = (uart_t *)(MMAP_UART0);
165 return readb(&uart->usr) & UART_USR_RXRDY;
168 int astro_get_char(void)
172 uart = (uart_t *)(MMAP_UART0);
173 while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
174 return readb(&uart->urb);
177 int misc_init_r(void)
181 puts("Configure Xilinx FPGA...");
182 retval = astro5373l_xilinx_load();
189 puts("Configure Altera FPGA...");
190 retval = astro5373l_altera_load();