board/armltd/vexpress64/pcie.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) ARM Ltd 2015
   4  *
   5  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <linux/bitops.h>
  13 #include <pci_ids.h>
  14 #include "pcie.h"
  15
  16 /* XpressRICH3 support */
  17 #define XR3_CONFIG_BASE                 0x7ff30000
  18 #define XR3_RESET_BASE                  0x7ff20000
  19
  20 #define XR3_PCI_ECAM_START              0x40000000
  21 #define XR3_PCI_ECAM_SIZE               28      /* as power of 2 = 0x10000000 */
  22 #define XR3_PCI_IOSPACE_START           0x5f800000
  23 #define XR3_PCI_IOSPACE_SIZE            23      /* as power of 2 = 0x800000 */
  24 #define XR3_PCI_MEMSPACE_START          0x50000000
  25 #define XR3_PCI_MEMSPACE_SIZE           27      /* as power of 2 = 0x8000000 */
  26 #define XR3_PCI_MEMSPACE64_START        0x4000000000
  27 #define XR3_PCI_MEMSPACE64_SIZE         33      /* as power of 2 = 0x200000000 */
  28
  29 #define JUNO_V2M_MSI_START              0x2c1c0000
  30 #define JUNO_V2M_MSI_SIZE               12      /* as power of 2 = 4096 */
  31
  32 #define XR3PCI_BASIC_STATUS             0x18
  33 #define XR3PCI_BS_GEN_MASK              (0xf << 8)
  34 #define XR3PCI_BS_LINK_MASK             0xff
  35
  36 #define XR3PCI_VIRTCHAN_CREDITS         0x90
  37 #define XR3PCI_BRIDGE_PCI_IDS           0x9c
  38 #define XR3PCI_PEX_SPC2                 0xd8
  39
  40 #define XR3PCI_ATR_PCIE_WIN0            0x600
  41 #define XR3PCI_ATR_PCIE_WIN1            0x700
  42 #define XR3PCI_ATR_AXI4_SLV0            0x800
  43
  44 #define XR3PCI_ATR_TABLE_SIZE           0x20
  45 #define XR3PCI_ATR_SRC_ADDR_LOW         0x0
  46 #define XR3PCI_ATR_SRC_ADDR_HIGH        0x4
  47 #define XR3PCI_ATR_TRSL_ADDR_LOW        0x8
  48 #define XR3PCI_ATR_TRSL_ADDR_HIGH       0xc
  49 #define XR3PCI_ATR_TRSL_PARAM           0x10
  50
  51 /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
  52 #define XR3PCI_ATR_TRSLID_AXIDEVICE     (0x420004)
  53 #define XR3PCI_ATR_TRSLID_AXIMEMORY     (0x4e0004)  /* Write-through, read/write allocate */
  54 #define XR3PCI_ATR_TRSLID_PCIE_CONF     (0x000001)
  55 #define XR3PCI_ATR_TRSLID_PCIE_IO       (0x020000)
  56 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY   (0x000000)
  57
  58 #define XR3PCI_ECAM_OFFSET(b, d, o)     (((b) << 20) | \
  59                                         (PCI_SLOT(d) << 15) | \
  60                                         (PCI_FUNC(d) << 12) | o)
  61
  62 #define JUNO_RESET_CTRL                 0x1004
  63 #define JUNO_RESET_CTRL_PHY             BIT(0)
  64 #define JUNO_RESET_CTRL_RC              BIT(1)
  65
  66 #define JUNO_RESET_STATUS               0x1008
  67 #define JUNO_RESET_STATUS_PLL           BIT(0)
  68 #define JUNO_RESET_STATUS_PHY           BIT(1)
  69 #define JUNO_RESET_STATUS_RC            BIT(2)
  70 #define JUNO_RESET_STATUS_MASK          (JUNO_RESET_STATUS_PLL | \
  71                                          JUNO_RESET_STATUS_PHY | \
  72                                          JUNO_RESET_STATUS_RC)
  73
  74 void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
  75                         unsigned long trsl_addr, int window_size,
  76                         int trsl_param)
  77 {
  78         /* X3PCI_ATR_SRC_ADDR_LOW:
  79              - bit 0: enable entry,
  80              - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
  81              - bits 7-11: reserved
  82              - bits 12-31: start of source address
  83         */
  84         writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
  85                base + XR3PCI_ATR_SRC_ADDR_LOW);
  86         writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
  87         writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
  88         writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
  89         writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
  90
  91         debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
  92                src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
  93                ((u64)1) << window_size, trsl_param);
  94 }
  95
  96 void xr3pci_setup_atr(void)
  97 {
  98         /* setup PCIe to CPU address translation tables */
  99         unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
 100
 101         /* forward all writes from PCIe to GIC V2M (used for MSI) */
 102         xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
 103                              JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
 104
 105         base += XR3PCI_ATR_TABLE_SIZE;
 106
 107         /* PCIe devices can write anywhere in memory */
 108         xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
 109                              31 /* grant access to all RAM under 4GB */,
 110                              XR3PCI_ATR_TRSLID_AXIMEMORY);
 111         base += XR3PCI_ATR_TABLE_SIZE;
 112         xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
 113                              XR3_PCI_MEMSPACE64_SIZE,
 114                              XR3PCI_ATR_TRSLID_AXIMEMORY);
 115
 116
 117         /* setup CPU to PCIe address translation table */
 118         base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
 119
 120         /* setup ECAM space to bus configuration interface */
 121         xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
 122                              XR3PCI_ATR_TRSLID_PCIE_CONF);
 123
 124         base += XR3PCI_ATR_TABLE_SIZE;
 125
 126         /* setup IO space translation */
 127         xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
 128                              XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
 129
 130         base += XR3PCI_ATR_TABLE_SIZE;
 131
 132         /* setup 32bit MEM space translation */
 133         xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
 134                              XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
 135
 136         base += XR3PCI_ATR_TABLE_SIZE;
 137
 138         /* setup 64bit MEM space translation */
 139         xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
 140                              XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
 141 }
 142
 143 void xr3pci_init(void)
 144 {
 145         u32 val;
 146         int timeout = 200;
 147
 148         /* Initialise the XpressRICH3 PCIe host bridge */
 149
 150         /* add credits */
 151         writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
 152         writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
 153         /* allow ECRC */
 154         writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
 155         /* setup the correct class code for the host bridge */
 156         writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
 157
 158         /* reset phy and root complex */
 159         writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
 160                XR3_RESET_BASE + JUNO_RESET_CTRL);
 161
 162         do {
 163                 mdelay(1);
 164                 val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
 165         } while (--timeout &&
 166                 (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
 167
 168         if (!timeout) {
 169                 printf("PCI XR3 Root complex reset timed out\n");
 170                 return;
 171         }
 172
 173         /* Wait for the link to train */
 174         mdelay(20);
 175         timeout = 20;
 176
 177         do {
 178                 mdelay(1);
 179                 val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
 180         } while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
 181
 182         if (!(val & XR3PCI_BS_LINK_MASK)) {
 183                 printf("Failed to negotiate a link!\n");
 184                 return;
 185         }
 186
 187         printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
 188                val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
 189
 190         xr3pci_setup_atr();
 191 }
 192
 193 void vexpress64_pcie_init(void)
 194 {
 195         xr3pci_init();
 196 }