1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Allied Telesis Labs
14 #include <linux/bitops.h>
15 #include <linux/mbus.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include "../common/gpio_hog.h"
21 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
22 #include <../serdes/a38x/high_speed_env_spec.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
28 #define CONFIG_NVS_LOCATION 0xf4800000
29 #define CONFIG_NVS_SIZE (512 << 10)
31 static struct serdes_map board_serdes_map[] = {
32 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
33 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
34 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
35 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
36 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
37 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
40 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
42 *serdes_map_array = board_serdes_map;
43 *count = ARRAY_SIZE(board_serdes_map);
48 * Define the DDR layout / topology here in the board file. This will
49 * be used by the DDR3 init code in the SPL U-Boot version to configure
50 * the DDR3 controller.
52 static struct mv_ddr_topology_map board_topology_map = {
54 0x1, /* active interfaces */
55 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
61 SPEED_BIN_DDR_1866M, /* speed_bin */
62 MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
63 MV_DDR_DIE_CAP_4GBIT, /* die capacity */
64 MV_DDR_FREQ_SAR, /* frequency */
65 0, 0, /* cas_l cas_wl */
66 MV_DDR_TEMP_LOW, /* temperature */
67 MV_DDR_TIM_2T} }, /* timing */
68 BUS_MASK_32BIT_ECC, /* subphys mask */
69 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
70 { {0} }, /* raw spd data */
71 {0}, /* timing parameters */
72 { {0} }, /* electrical configuration */
73 {0}, /* electrical parameters */
74 0, /* Clock enable mask */
78 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
80 /* Return the board topology as defined in the board code */
81 return &board_topology_map;
84 int board_early_init_f(void)
87 writel(0x00001111, MVEBU_MPP_BASE + 0x00);
88 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
89 writel(0x55000000, MVEBU_MPP_BASE + 0x08);
90 writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
91 writel(0x55555555, MVEBU_MPP_BASE + 0x10);
92 writel(0x00100565, MVEBU_MPP_BASE + 0x14);
93 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
94 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
99 void spl_board_init(void)
105 /* address of boot parameters */
106 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
109 mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
110 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
112 /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
113 writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
120 void arch_preboot_os(void)
122 #ifdef CONFIG_WATCHDOG
123 wdt_stop(gd->watchdog_dev);
127 static int led_7seg_init(unsigned int segments)
132 struct gpio_desc desc[8];
134 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
139 ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
140 "segment-gpios", desc,
141 ARRAY_SIZE(desc), GPIOD_IS_OUT);
145 for (i = 0; i < ARRAY_SIZE(desc); i++) {
146 ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
154 #ifdef CONFIG_MISC_INIT_R
155 int misc_init_r(void)
157 static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
160 gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
161 gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
162 gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
163 gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
165 #ifdef MTDPARTS_MTDOOPS
166 env_set("mtdoops", MTDPARTS_MTDOOPS);
175 #ifdef CONFIG_DISPLAY_BOARDINFO
178 puts("Board: " CONFIG_SYS_BOARD "\n");