board/advantech/dms-ba16/dms-ba16.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Timesys Corporation
   4  * Copyright 2016 Advantech Corporation
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <linux/errno.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/mxc_i2c.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <i2c.h>
  29 #include <input.h>
  30 #include <pwm.h>
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  34         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  35         PAD_CTL_HYS)
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  42         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  46         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  47
  48 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  49         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  50
  51 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  52         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  53
  54 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  55                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  56
  57 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  58         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  59         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  60
  61 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  62
  63 int dram_init(void)
  64 {
  65         gd->ram_size = imx_ddr_size();
  66
  67         return 0;
  68 }
  69
  70 static iomux_v3_cfg_t const uart3_pads[] = {
  71         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  72         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  73         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  75 };
  76
  77 static iomux_v3_cfg_t const uart4_pads[] = {
  78         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80 };
  81
  82 static iomux_v3_cfg_t const enet_pads[] = {
  83         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  92         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  93         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  94         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  95         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  96         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  97         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  98         /* AR8033 PHY Reset */
  99         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 100 };
 101
 102 static void setup_iomux_enet(void)
 103 {
 104         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 105
 106         /* Reset AR8033 PHY */
 107         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 108         mdelay(10);
 109         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 110         mdelay(1);
 111 }
 112
 113 static iomux_v3_cfg_t const usdhc2_pads[] = {
 114         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 121 };
 122
 123 static iomux_v3_cfg_t const usdhc3_pads[] = {
 124         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135 };
 136
 137 static iomux_v3_cfg_t const usdhc4_pads[] = {
 138         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 149         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 150 };
 151
 152 static iomux_v3_cfg_t const ecspi1_pads[] = {
 153         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 154         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 155         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 156         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 157 };
 158
 159 static struct i2c_pads_info i2c_pad_info1 = {
 160         .scl = {
 161                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 162                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 163                 .gp = IMX_GPIO_NR(5, 27)
 164         },
 165         .sda = {
 166                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 167                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 168                 .gp = IMX_GPIO_NR(5, 26)
 169         }
 170 };
 171
 172 static struct i2c_pads_info i2c_pad_info2 = {
 173         .scl = {
 174                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 175                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 176                 .gp = IMX_GPIO_NR(4, 12)
 177         },
 178         .sda = {
 179                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 180                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 181                 .gp = IMX_GPIO_NR(4, 13)
 182         }
 183 };
 184
 185 static struct i2c_pads_info i2c_pad_info3 = {
 186         .scl = {
 187                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 188                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 189                 .gp = IMX_GPIO_NR(1, 3)
 190         },
 191         .sda = {
 192                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 193                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 194                 .gp = IMX_GPIO_NR(1, 6)
 195         }
 196 };
 197
 198 #ifdef CONFIG_MXC_SPI
 199 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 200 {
 201         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 202 }
 203
 204 static void setup_spi(void)
 205 {
 206         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 207 }
 208 #endif
 209
 210 static iomux_v3_cfg_t const pcie_pads[] = {
 211         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 212         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 213 };
 214
 215 static void setup_pcie(void)
 216 {
 217         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 218 }
 219
 220 static void setup_iomux_uart(void)
 221 {
 222         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 223         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 224 }
 225
 226 #ifdef CONFIG_FSL_ESDHC_IMX
 227 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 228         {USDHC2_BASE_ADDR},
 229         {USDHC3_BASE_ADDR},
 230         {USDHC4_BASE_ADDR},
 231 };
 232
 233 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 234 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 235
 236 int board_mmc_getcd(struct mmc *mmc)
 237 {
 238         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 239         int ret = 0;
 240
 241         switch (cfg->esdhc_base) {
 242         case USDHC2_BASE_ADDR:
 243                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 244                 break;
 245         case USDHC3_BASE_ADDR:
 246                 ret = 1; /* eMMC is always present */
 247                 break;
 248         case USDHC4_BASE_ADDR:
 249                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 250                 break;
 251         }
 252
 253         return ret;
 254 }
 255
 256 int board_mmc_init(bd_t *bis)
 257 {
 258         int ret;
 259         int i;
 260
 261         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 262                 switch (i) {
 263                 case 0:
 264                         imx_iomux_v3_setup_multiple_pads(
 265                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 266                         gpio_direction_input(USDHC2_CD_GPIO);
 267                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 268                         break;
 269                 case 1:
 270                         imx_iomux_v3_setup_multiple_pads(
 271                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 272                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 273                         break;
 274                 case 2:
 275                         imx_iomux_v3_setup_multiple_pads(
 276                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 277                         gpio_direction_input(USDHC4_CD_GPIO);
 278                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 279                         break;
 280                 default:
 281                         printf("Warning: you configured more USDHC controllers\n"
 282                                "(%d) then supported by the board (%d)\n",
 283                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 284                         return -EINVAL;
 285                 }
 286
 287                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 288                 if (ret)
 289                         return ret;
 290         }
 291
 292         return 0;
 293 }
 294 #endif
 295
 296 static int mx6_rgmii_rework(struct phy_device *phydev)
 297 {
 298         /* set device address 0x7 */
 299         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 300         /* offset 0x8016: CLK_25M Clock Select */
 301         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 302         /* enable register write, no post increment, address 0x7 */
 303         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 304         /* set to 125 MHz from local PLL source */
 305         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 306         /* set debug port address: SerDes Test and System Mode Control */
 307         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 308         /* enable rgmii tx clock delay */
 309         /* set the reserved bits to avoid board specific voltage peak issue*/
 310         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 311
 312         return 0;
 313 }
 314
 315 int board_phy_config(struct phy_device *phydev)
 316 {
 317         mx6_rgmii_rework(phydev);
 318
 319         if (phydev->drv->config)
 320                 phydev->drv->config(phydev);
 321
 322         return 0;
 323 }
 324
 325 #if defined(CONFIG_VIDEO_IPUV3)
 326 static iomux_v3_cfg_t const backlight_pads[] = {
 327         /* Power for LVDS Display */
 328         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 329 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 330         /* Backlight enable for LVDS display */
 331         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 332 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 333         /* backlight PWM brightness control */
 334         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 335 };
 336
 337 static void do_enable_hdmi(struct display_info_t const *dev)
 338 {
 339         imx_enable_hdmi_phy();
 340 }
 341
 342 int board_cfb_skip(void)
 343 {
 344         gpio_direction_output(LVDS_POWER_GP, 1);
 345
 346         return 0;
 347 }
 348
 349 static int detect_baseboard(struct display_info_t const *dev)
 350 {
 351         return 0 == dev->addr;
 352 }
 353
 354 struct display_info_t const displays[] = {{
 355         .bus    = -1,
 356         .addr   = 0,
 357         .pixfmt = IPU_PIX_FMT_RGB24,
 358         .detect = detect_baseboard,
 359         .enable = NULL,
 360         .mode   = {
 361                 .name           = "SHARP-LQ156M1LG21",
 362                 .refresh        = 60,
 363                 .xres           = 1920,
 364                 .yres           = 1080,
 365                 .pixclock       = 7851,
 366                 .left_margin    = 100,
 367                 .right_margin   = 40,
 368                 .upper_margin   = 30,
 369                 .lower_margin   = 3,
 370                 .hsync_len      = 10,
 371                 .vsync_len      = 2,
 372                 .sync           = FB_SYNC_EXT,
 373                 .vmode          = FB_VMODE_NONINTERLACED
 374 } }, {
 375         .bus    = -1,
 376         .addr   = 3,
 377         .pixfmt = IPU_PIX_FMT_RGB24,
 378         .detect = detect_hdmi,
 379         .enable = do_enable_hdmi,
 380         .mode   = {
 381                 .name           = "HDMI",
 382                 .refresh        = 60,
 383                 .xres           = 1024,
 384                 .yres           = 768,
 385                 .pixclock       = 15385,
 386                 .left_margin    = 220,
 387                 .right_margin   = 40,
 388                 .upper_margin   = 21,
 389                 .lower_margin   = 7,
 390                 .hsync_len      = 60,
 391                 .vsync_len      = 10,
 392                 .sync           = FB_SYNC_EXT,
 393                 .vmode          = FB_VMODE_NONINTERLACED
 394 } } };
 395 size_t display_count = ARRAY_SIZE(displays);
 396
 397 static void setup_display(void)
 398 {
 399         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 400         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 401
 402         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 403
 404         imx_setup_hdmi();
 405
 406         /* Set LDB_DI0 as clock source for IPU_DI0 */
 407         clrsetbits_le32(&mxc_ccm->chsccdr,
 408                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 409                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 410                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 411
 412         /* Turn on IPU LDB DI0 clocks */
 413         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 414
 415         enable_ipu_clock();
 416
 417         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 418                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
 419                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 420                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 421                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 422                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 423                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 424                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 425                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 426                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 427                &iomux->gpr[2]);
 428
 429         clrsetbits_le32(&iomux->gpr[3],
 430                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 431                         IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 432                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 433                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 434                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 435
 436         /* backlights off until needed */
 437         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 438                                          ARRAY_SIZE(backlight_pads));
 439
 440         gpio_direction_input(LVDS_POWER_GP);
 441         gpio_direction_input(LVDS_BACKLIGHT_GP);
 442 }
 443 #endif /* CONFIG_VIDEO_IPUV3 */
 444
 445 /*
 446  * Do not overwrite the console
 447  * Use always serial for U-Boot console
 448  */
 449 int overwrite_console(void)
 450 {
 451         return 1;
 452 }
 453
 454 int board_eth_init(bd_t *bis)
 455 {
 456         setup_iomux_enet();
 457         setup_pcie();
 458
 459         return cpu_eth_init(bis);
 460 }
 461
 462 static iomux_v3_cfg_t const misc_pads[] = {
 463         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 464         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 465         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 466         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 467         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 468         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 469         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 470 };
 471 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 472 #define WIFI_EN IMX_GPIO_NR(6, 14)
 473
 474 int setup_ba16_sata(void)
 475 {
 476         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 477         int ret;
 478
 479         ret = enable_sata_clock();
 480         if (ret)
 481                 return ret;
 482
 483         clrsetbits_le32(&iomuxc_regs->gpr[13],
 484                         IOMUXC_GPR13_SATA_MASK,
 485                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 486                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 487                         |IOMUXC_GPR13_SATA_SPEED_3G
 488                         |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 489                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 490                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
 491                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
 492                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
 493                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 494
 495         return 0;
 496 }
 497
 498 int board_early_init_f(void)
 499 {
 500         imx_iomux_v3_setup_multiple_pads(misc_pads,
 501                                          ARRAY_SIZE(misc_pads));
 502
 503         setup_iomux_uart();
 504
 505 #if defined(CONFIG_VIDEO_IPUV3)
 506         /* Set LDB clock to PLL2 PFD0 */
 507         select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
 508 #endif
 509         return 0;
 510 }
 511
 512 int board_init(void)
 513 {
 514         gpio_direction_output(SUS_S3_OUT, 1);
 515         gpio_direction_output(WIFI_EN, 1);
 516 #if defined(CONFIG_VIDEO_IPUV3)
 517         setup_display();
 518 #endif
 519         /* address of boot parameters */
 520         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 521
 522 #ifdef CONFIG_MXC_SPI
 523         setup_spi();
 524 #endif
 525         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 526         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 527         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 528
 529         return 0;
 530 }
 531
 532 #ifdef CONFIG_CMD_BMODE
 533 static const struct boot_mode board_boot_modes[] = {
 534         /* 4 bit bus width */
 535         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 536         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 537         {NULL,   0},
 538 };
 539 #endif
 540
 541 void pmic_init(void)
 542 {
 543
 544 #define DA9063_ADDR 0x58
 545 #define BCORE2_CONF 0x9D
 546 #define BCORE1_CONF 0x9E
 547 #define BPRO_CONF 0x9F
 548 #define BIO_CONF 0xA0
 549 #define BMEM_CONF 0xA1
 550 #define BPERI_CONF 0xA2
 551 #define MODE_BIT_H 7
 552 #define MODE_BIT_L 6
 553
 554         uchar val;
 555         i2c_set_bus_num(2);
 556
 557         i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
 558         val |= (1 << MODE_BIT_H);
 559         val &= ~(1 << MODE_BIT_L);
 560         i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
 561
 562         i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
 563         val |= (1 << MODE_BIT_H);
 564         val &= ~(1 << MODE_BIT_L);
 565         i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
 566
 567         i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
 568         val |= (1 << MODE_BIT_H);
 569         val &= ~(1 << MODE_BIT_L);
 570         i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
 571
 572         i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
 573         val |= (1 << MODE_BIT_H);
 574         val &= ~(1 << MODE_BIT_L);
 575         i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
 576
 577         i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
 578         val |= (1 << MODE_BIT_H);
 579         val &= ~(1 << MODE_BIT_L);
 580         i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
 581
 582         i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
 583         val |= (1 << MODE_BIT_H);
 584         val &= ~(1 << MODE_BIT_L);
 585         i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
 586
 587 }
 588
 589 int board_late_init(void)
 590 {
 591 #ifdef CONFIG_CMD_BMODE
 592         add_board_boot_modes(board_boot_modes);
 593 #endif
 594
 595 #if defined(CONFIG_VIDEO_IPUV3)
 596         /*
 597          * We need at least 200ms between power on and backlight on
 598          * as per specifications from CHI MEI
 599          */
 600         mdelay(250);
 601
 602         /* enable backlight PWM 1 */
 603         pwm_init(0, 0, 0);
 604
 605         /* duty cycle 5000000ns, period: 5000000ns */
 606         pwm_config(0, 5000000, 5000000);
 607
 608         /* Backlight Power */
 609         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 610
 611         pwm_enable(0);
 612 #endif
 613
 614 #ifdef CONFIG_SATA
 615         setup_ba16_sata();
 616 #endif
 617
 618         /* board specific pmic init */
 619         pmic_init();
 620
 621         return 0;
 622 }
 623
 624 int checkboard(void)
 625 {
 626         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 627         return 0;
 628 }