board/Synology/ds414/ds414.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *
   4  * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <miiphy.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/soc.h>
  13 #include <linux/bitops.h>
  14 #include <linux/mbus.h>
  15
  16 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  17 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  18 #include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
  23
  24 #define DS414_GPP_OUT_VAL_LOW           (BIT(25) | BIT(30))
  25 #define DS414_GPP_OUT_VAL_MID           (BIT(10) | BIT(15))
  26 #define DS414_GPP_OUT_VAL_HIGH          (0)
  27
  28 #define DS414_GPP_OUT_POL_LOW           (0)
  29 #define DS414_GPP_OUT_POL_MID           (0)
  30 #define DS414_GPP_OUT_POL_HIGH          (0)
  31
  32 #define DS414_GPP_OUT_ENA_LOW           (~(BIT(25) | BIT(30)))
  33 #define DS414_GPP_OUT_ENA_MID           (~(BIT(10) | BIT(12) | \
  34                                            BIT(13) | BIT(14) | BIT(15)))
  35 #define DS414_GPP_OUT_ENA_HIGH          (~0)
  36
  37 static const u32 ds414_mpp_control[] = {
  38         0x11111111,
  39         0x22221111,
  40         0x22222222,
  41         0x00000000,
  42         0x11110000,
  43         0x00004000,
  44         0x00000000,
  45         0x00000000,
  46         0x00000000
  47 };
  48
  49 /* DDR3 static MC configuration */
  50
  51 /* 1G_v1 (4x2Gbits) adapted by DS414 */
  52 MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
  53         {0x00001400, 0x73014A28},       /*DDR SDRAM Configuration Register */
  54         {0x00001404, 0x30000800},       /*Dunit Control Low Register */
  55         {0x00001408, 0x44148887},       /*DDR SDRAM Timing (Low) Register */
  56         {0x0000140C, 0x3AD83FEA},       /*DDR SDRAM Timing (High) Register */
  57
  58         {0x00001410, 0x14000000},       /*DDR SDRAM Address Control Register */
  59
  60         {0x00001414, 0x00000000},       /*DDR SDRAM Open Pages Control Register */
  61         {0x00001418, 0x00000e00},       /*DDR SDRAM Operation Register */
  62         {0x00001420, 0x00000004},       /*DDR SDRAM Extended Mode Register */
  63         {0x00001424, 0x0000F3FF},       /*Dunit Control High Register */
  64         {0x00001428, 0x000F8830},       /*Dunit Control High Register */
  65         {0x0000142C, 0x054C36F4},       /*Dunit Control High Register */
  66         {0x0000147C, 0x0000C671},
  67
  68         {0x000014a0, 0x00000001},
  69         {0x000014a8, 0x00000100},       /*2:1 */
  70         {0x00020220, 0x00000006},
  71
  72         {0x00001494, 0x00010000},       /*DDR SDRAM ODT Control (Low) Register */
  73         {0x00001498, 0x00000000},       /*DDR SDRAM ODT Control (High) Register */
  74         {0x0000149C, 0x00000001},       /*DDR Dunit ODT Control Register */
  75
  76         {0x000014C0, 0x192424C9},       /* DRAM address and Control Driving Strenght  */
  77         {0x000014C4, 0x0AAA24C9},       /* DRAM Data and DQS Driving Strenght  */
  78
  79         {0x000200e8, 0x3FFF0E01},       /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
  80         {0x00020184, 0x3FFFFFE0},       /* DO NOT Modify - Close fast path Window to - 2G */
  81
  82         {0x0001504, 0x3FFFFFE1},        /* CS0 Size */
  83         {0x000150C, 0x00000000},        /* CS1 Size */
  84         {0x0001514, 0x00000000},        /* CS2 Size */
  85         {0x000151C, 0x00000000},        /* CS3 Size */
  86
  87         {0x00001538, 0x00000009},       /*Read Data Sample Delays Register */
  88         {0x0000153C, 0x00000009},       /*Read Data Ready Delay Register */
  89
  90         {0x000015D0, 0x00000650},       /*MR0 */
  91         {0x000015D4, 0x00000044},       /*MR1 */
  92         {0x000015D8, 0x00000010},       /*MR2 */
  93         {0x000015DC, 0x00000000},       /*MR3 */
  94
  95         {0x000015E4, 0x00203c18},       /*ZQC Configuration Register */
  96         {0x000015EC, 0xF800A225},       /*DDR PHY */
  97
  98         {0x0, 0x0}
  99 };
 100
 101 MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
 102         {"ds414_1333-667",   0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1,  NULL},
 103 };
 104
 105 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
 106
 107 MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
 108         { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
 109           { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
 110             PEX_BUS_DISABLED },
 111           0x0040, serdes_change_m_phy
 112         }
 113 };
 114
 115 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 116 {
 117         return &ds414_ddr_modes[0];
 118 }
 119
 120 MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
 121 {
 122         return &ds414_serdes_cfg[0];
 123 }
 124
 125 u8 board_sat_r_get(u8 dev_num, u8 reg)
 126 {
 127         return 0xf;     /* All PEX ports support PCIe Gen2 */
 128 }
 129
 130 int board_early_init_f(void)
 131 {
 132         int i;
 133
 134         /* Set GPP Out value */
 135         reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
 136         reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
 137         reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
 138
 139         /* set GPP polarity */
 140         reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
 141         reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
 142         reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
 143
 144         /* Set GPP Out Enable */
 145         reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
 146         reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
 147         reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
 148
 149         for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
 150                 reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
 151
 152         return 0;
 153 }
 154
 155 int board_init(void)
 156 {
 157         u32 pwr_mng_ctrl_reg;
 158
 159         /* Adress of boot parameters */
 160         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 161
 162         /* Gate unused clocks
 163          *
 164          * Note: Disabling unused PCIe lanes will hang PCI bus scan.
 165          *       Once this is resolved, bits 10-12, 26 and 27 can be
 166          *       unset here as well.
 167          */
 168         pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
 169         pwr_mng_ctrl_reg &= ~(BIT(0));                          /* Audio */
 170         pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2));                 /* GE3, GE2 */
 171         pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15));               /* SATA0 link and core */
 172         pwr_mng_ctrl_reg &= ~(BIT(16));                         /* LCD */
 173         pwr_mng_ctrl_reg &= ~(BIT(17));                         /* SDIO */
 174         pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20));               /* USB1 and USB2 */
 175         pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30));               /* SATA1 link and core */
 176         reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
 177
 178         return 0;
 179 }
 180
 181 int checkboard(void)
 182 {
 183         puts("Board: DS414\n");
 184
 185         return 0;
 186 }