board/Synology/ds109/ds109.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2009-2012
   4  * Wojciech Dubowik <wojciech.dubowik@neratec.com>
   5  * Luka Perkov <luka@openwrt.org>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <miiphy.h>
  11 #include <net.h>
  12 #include <asm/setup.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/soc.h>
  15 #include <asm/arch/mpp.h>
  16 #include "ds109.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 int board_early_init_f(void)
  21 {
  22         /*
  23          * default gpio configuration
  24          * There are maximum 64 gpios controlled through 2 sets of registers
  25          * the below configuration configures mainly initial LED status
  26          */
  27         mvebu_config_gpio(DS109_OE_VAL_LOW,
  28                           DS109_OE_VAL_HIGH,
  29                           DS109_OE_LOW, DS109_OE_HIGH);
  30
  31         /* Multi-Purpose Pins Functionality configuration */
  32         static const u32 kwmpp_config[] = {
  33                 MPP0_SPI_SCn,           /* SPI Flash */
  34                 MPP1_SPI_MOSI,
  35                 MPP2_SPI_SCK,
  36                 MPP3_SPI_MISO,
  37                 MPP4_GPIO,
  38                 MPP5_GPO,
  39                 MPP6_SYSRST_OUTn,       /* Reset signal */
  40                 MPP7_GPO,
  41                 MPP8_TW_SDA,            /* I2C */
  42                 MPP9_TW_SCK,            /* I2C */
  43                 MPP10_UART0_TXD,
  44                 MPP11_UART0_RXD,
  45                 MPP12_GPO,
  46                 MPP13_UART1_TXD,
  47                 MPP14_UART1_RXD,
  48                 MPP15_GPIO,
  49                 MPP16_GPIO,
  50                 MPP17_GPIO,
  51                 MPP18_GPO,
  52                 MPP19_GPO,
  53                 MPP20_SATA1_ACTn,
  54                 MPP21_SATA0_ACTn,
  55                 MPP22_GPIO,             /* HDD2 FAIL LED */
  56                 MPP23_GPIO,             /* HDD1 FAIL LED */
  57                 MPP24_GPIO,
  58                 MPP25_GPIO,
  59                 MPP26_GPIO,
  60                 MPP27_GPIO,
  61                 MPP28_GPIO,
  62                 MPP29_GPIO,
  63                 MPP30_GPIO,
  64                 MPP31_GPIO,             /* HDD2 */
  65                 MPP32_GPIO,             /* FAN A */
  66                 MPP33_GPIO,             /* FAN B */
  67                 MPP34_GPIO,             /* FAN C */
  68                 MPP35_GPIO,             /* FAN SENSE */
  69                 MPP36_GPIO,
  70                 MPP37_GPIO,
  71                 MPP38_GPIO,
  72                 MPP39_GPIO,
  73                 MPP40_GPIO,
  74                 MPP41_GPIO,
  75                 MPP42_GPIO,
  76                 MPP43_GPIO,
  77                 MPP44_GPIO,
  78                 MPP45_GPIO,
  79                 MPP46_GPIO,
  80                 MPP47_GPIO,
  81                 MPP48_GPIO,
  82                 MPP49_GPIO,
  83                 0
  84         };
  85         kirkwood_mpp_conf(kwmpp_config, NULL);
  86         return 0;
  87 }
  88
  89 int board_init(void)
  90 {
  91         /* address of boot parameters */
  92         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  93
  94         return 0;
  95 }
  96
  97 /* Synology reset uses UART */
  98 #include <ns16550.h>
  99 #define SOFTWARE_SHUTDOWN   0x31
 100 #define SOFTWARE_REBOOT     0x43
 101 #define CONFIG_SYS_NS16550_COM2         KW_UART1_BASE
 102 void reset_misc(void)
 103 {
 104         int b_d;
 105         printf("Synology reset...");
 106         udelay(50000);
 107
 108         b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
 109                 CONFIG_SYS_NS16550_CLK, 9600);
 110         NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
 111         NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
 112 }
 113
 114 /* Support old kernels */
 115 void setup_board_tags(struct tag **in_params)
 116 {
 117         unsigned int boardId;
 118         struct tag *params;
 119         struct tag_mv_uboot *t;
 120         int i;
 121
 122         printf("Synology board tags...");
 123         params = *in_params;
 124         t = (struct tag_mv_uboot *)&params->u;
 125
 126         t->uboot_version = VER_NUM;
 127
 128         boardId = SYNO_DS109_ID;
 129         t->uboot_version |= boardId;
 130
 131         t->tclk = CONFIG_SYS_TCLK;
 132         t->sysclk = CONFIG_SYS_TCLK*2;
 133
 134         t->isusbhost = 1;
 135         for (i = 0; i < 4; i++) {
 136                 memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
 137                 t->mtu[i] = 0;
 138         }
 139
 140         params->hdr.tag = ATAG_MV_UBOOT;
 141         params->hdr.size = tag_size(tag_mv_uboot);
 142         params = tag_next(params);
 143         *in_params = params;
 144 }
 145
 146 #ifdef CONFIG_RESET_PHY_R
 147 /* Configure and enable MV88E1116 PHY */
 148 void reset_phy(void)
 149 {
 150         u16 reg;
 151         u16 devadr;
 152         char *name = "egiga0";
 153
 154         if (miiphy_set_current_dev(name))
 155                 return;
 156
 157         /* command to read PHY dev address */
 158         if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
 159                 printf("Error: 88E1116 could not read PHY dev address\n");
 160                 return;
 161         }
 162
 163         /*
 164          * Enable RGMII delay on Tx and Rx for CPU port
 165          * Ref: sec 4.7.2 of chip datasheet
 166          */
 167         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 168         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 169         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 170         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 171         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 172
 173         /* reset the phy */
 174         miiphy_reset(name, devadr);
 175
 176         printf("88E1116 Initialized on %s\n", name);
 177 }
 178 #endif /* CONFIG_RESET_PHY_R */