board/Marvell/guruplug/guruplug.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Siddarth Gore <gores@marvell.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301 USA
  23  */
  24
  25 #include <common.h>
  26 #include <miiphy.h>
  27 #include <asm/arch/kirkwood.h>
  28 #include <asm/arch/mpp.h>
  29 #include "guruplug.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int board_init(void)
  34 {
  35         /*
  36          * default gpio configuration
  37          * There are maximum 64 gpios controlled through 2 sets of registers
  38          * the  below configuration configures mainly initial LED status
  39          */
  40         kw_config_gpio(GURUPLUG_OE_VAL_LOW,
  41                         GURUPLUG_OE_VAL_HIGH,
  42                         GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
  43
  44         /* Multi-Purpose Pins Functionality configuration */
  45         u32 kwmpp_config[] = {
  46                 MPP0_NF_IO2,
  47                 MPP1_NF_IO3,
  48                 MPP2_NF_IO4,
  49                 MPP3_NF_IO5,
  50                 MPP4_NF_IO6,
  51                 MPP5_NF_IO7,
  52                 MPP6_SYSRST_OUTn,
  53                 MPP7_GPO,       /* GPIO_RST */
  54                 MPP8_TW_SDA,
  55                 MPP9_TW_SCK,
  56                 MPP10_UART0_TXD,
  57                 MPP11_UART0_RXD,
  58                 MPP12_SD_CLK,
  59                 MPP13_SD_CMD,
  60                 MPP14_SD_D0,
  61                 MPP15_SD_D1,
  62                 MPP16_SD_D2,
  63                 MPP17_SD_D3,
  64                 MPP18_NF_IO0,
  65                 MPP19_NF_IO1,
  66                 MPP20_GE1_0,
  67                 MPP21_GE1_1,
  68                 MPP22_GE1_2,
  69                 MPP23_GE1_3,
  70                 MPP24_GE1_4,
  71                 MPP25_GE1_5,
  72                 MPP26_GE1_6,
  73                 MPP27_GE1_7,
  74                 MPP28_GE1_8,
  75                 MPP29_GE1_9,
  76                 MPP30_GE1_10,
  77                 MPP31_GE1_11,
  78                 MPP32_GE1_12,
  79                 MPP33_GE1_13,
  80                 MPP34_GE1_14,
  81                 MPP35_GE1_15,
  82                 MPP36_GPIO,
  83                 MPP37_GPIO,
  84                 MPP38_GPIO,
  85                 MPP39_GPIO,
  86                 MPP40_TDM_SPI_SCK,
  87                 MPP41_TDM_SPI_MISO,
  88                 MPP42_TDM_SPI_MOSI,
  89                 MPP43_GPIO,
  90                 MPP44_GPIO,
  91                 MPP45_GPIO,
  92                 MPP46_GPIO,     /* M_RLED */
  93                 MPP47_GPIO,     /* M_GLED */
  94                 MPP48_GPIO,     /* B_RLED */
  95                 MPP49_GPIO,     /* B_GLED */
  96                 0
  97         };
  98         kirkwood_mpp_conf(kwmpp_config);
  99
 100         /*
 101          * arch number of board
 102          */
 103         gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
 104
 105         /* adress of boot parameters */
 106         gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 107
 108         return 0;
 109 }
 110
 111 int dram_init(void)
 112 {
 113         int i;
 114
 115         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 116                 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
 117                 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
 118         }
 119         return 0;
 120 }
 121
 122 #ifdef CONFIG_RESET_PHY_R
 123 void mv_phy_88e1121_init(char *name)
 124 {
 125         u16 reg;
 126         u16 devadr;
 127
 128         if (miiphy_set_current_dev(name))
 129                 return;
 130
 131         /* command to read PHY dev address */
 132         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 133                 printf("Err..%s could not read PHY dev address\n",
 134                         __FUNCTION__);
 135                 return;
 136         }
 137
 138         /*
 139          * Enable RGMII delay on Tx and Rx for CPU port
 140          * Ref: sec 4.7.2 of chip datasheet
 141          */
 142         miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
 143         miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
 144         reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
 145         miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
 146         miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
 147
 148         /* reset the phy */
 149         miiphy_reset(name, devadr);
 150
 151         printf("88E1121 Initialized on %s\n", name);
 152 }
 153
 154 void reset_phy(void)
 155 {
 156         /* configure and initialize both PHY's */
 157         mv_phy_88e1121_init("egiga0");
 158         mv_phy_88e1121_init("egiga1");
 159 }
 160 #endif /* CONFIG_RESET_PHY_R */