1 // SPDX-License-Identifier: GPL-2.0+
4 * eInfochips Ltd. <www.einfochips.com>
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
9 * Marvell Semiconductor <www.marvell.com>
10 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 * Contributor: Mahavir Jain <mjain@marvell.com>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/mfp.h>
20 #include <asm/arch/armada100.h>
23 #include <asm/mach-types.h>
24 #include <linux/delay.h>
26 #ifdef CONFIG_ARMADA100_FEC
29 #endif /* CONFIG_ARMADA100_FEC */
31 DECLARE_GLOBAL_DATA_PTR;
33 int board_early_init_f(void)
40 /* Enable Console on UART3 */
44 /* Ethernet PHY Interface */
69 MFP_EOC /*End of configuration*/
78 struct armd1apb2_registers *apb2_regs =
79 (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
81 /* arch number of Board */
82 gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
83 /* adress of boot parameters */
84 gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
86 gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
88 /* Deassert PHY_RST# */
89 gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
91 /* Enable SSP2 clock */
92 writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
96 #ifdef CONFIG_ARMADA100_FEC
97 int board_eth_init(bd_t *bis)
99 struct armd1apmu_registers *apmu_regs =
100 (struct armd1apmu_registers *)ARMD1_APMU_BASE;
102 /* Enable clock of ethernet controller */
103 writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
105 return armada100_fec_register(ARMD1_FEC_BASE);
108 #ifdef CONFIG_RESET_PHY_R
109 /* Configure and initialize PHY chip 88E3015 */
113 const char *name = "armd-fec0";
115 if (miiphy_set_current_dev(name))
118 /* command to read PHY dev address */
119 if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
120 printf("Err..%s could not read PHY dev address\n", __func__);
124 /* Set Ethernet LED in TX blink mode */
125 miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
126 miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
129 miiphy_reset(name, phy_adr);
130 debug("88E3015 Initialized on %s\n", name);
132 #endif /* CONFIG_RESET_PHY_R */
133 #endif /* CONFIG_ARMADA100_FEC */