board/CarMediaLab/flea3/flea3.c

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   5  *
   6  * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <linux/errno.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/iomux-mx35.h>
  17 #include <i2c.h>
  18 #include <linux/types.h>
  19 #include <asm/gpio.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <netdev.h>
  22 #include <fdt_support.h>
  23 #include <mtd_node.h>
  24 #include <jffs2/load_kernel.h>
  25
  26 #ifndef CONFIG_BOARD_EARLY_INIT_F
  27 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  28 #endif
  29
  30 #define CCM_CCMR_CONFIG         0x003F4208
  31
  32 #define ESDCTL_DDR2_CONFIG      0x007FFC3F
  33 #define ESDCTL_0x92220000       0x92220000
  34 #define ESDCTL_0xA2220000       0xA2220000
  35 #define ESDCTL_0xB2220000       0xB2220000
  36 #define ESDCTL_0x82228080       0x82228080
  37 #define ESDCTL_DDR2_EMR2        0x04000000
  38 #define ESDCTL_DDR2_EMR3        0x06000000
  39 #define ESDCTL_PRECHARGE        0x00000400
  40 #define ESDCTL_DDR2_EN_DLL      0x02000400
  41 #define ESDCTL_DDR2_RESET_DLL   0x00000333
  42 #define ESDCTL_DDR2_MR          0x00000233
  43 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
  44 #define ESDCTL_DELAY_LINE5      0x00F49F00
  45
  46 static inline void dram_wait(unsigned int count)
  47 {
  48         volatile unsigned int wait = count;
  49
  50         while (wait--)
  51                 ;
  52 }
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 int dram_init(void)
  57 {
  58         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
  59                 PHYS_SDRAM_1_SIZE);
  60
  61         return 0;
  62 }
  63
  64 static void board_setup_sdram_bank(u32 start_address)
  65
  66 {
  67         struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  68         u32 *cfg_reg, *ctl_reg;
  69         u32 val;
  70
  71         switch (start_address) {
  72         case CSD0_BASE_ADDR:
  73                 cfg_reg = &esdc->esdcfg0;
  74                 ctl_reg = &esdc->esdctl0;
  75                 break;
  76         case CSD1_BASE_ADDR:
  77                 cfg_reg = &esdc->esdcfg1;
  78                 ctl_reg = &esdc->esdctl1;
  79                 break;
  80         default:
  81                 return;
  82         }
  83
  84         /* Initialize MISC register for DDR2 */
  85         val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
  86                 ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
  87         writel(val, &esdc->esdmisc);
  88         val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
  89         writel(val, &esdc->esdmisc);
  90
  91         /*
  92          * according to DDR2 specs, wait a while before
  93          * the PRECHARGE_ALL command
  94          */
  95         dram_wait(0x20000);
  96
  97         /* Load DDR2 config and timing */
  98         writel(ESDCTL_DDR2_CONFIG, cfg_reg);
  99
 100         /* Precharge ALL */
 101         writel(ESDCTL_0x92220000,
 102                 ctl_reg);
 103         writel(0xda, start_address + ESDCTL_PRECHARGE);
 104
 105         /* Load mode */
 106         writel(ESDCTL_0xB2220000,
 107                 ctl_reg);
 108         writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
 109         writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
 110         writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
 111         writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
 112
 113         /* Precharge ALL */
 114         writel(ESDCTL_0x92220000,
 115                 ctl_reg);
 116         writel(0xda, start_address + ESDCTL_PRECHARGE);
 117
 118         /* Set mode auto refresh : at least two refresh are required */
 119         writel(ESDCTL_0xA2220000,
 120                 ctl_reg);
 121         writel(0xda, start_address);
 122         writel(0xda, start_address);
 123
 124         writel(ESDCTL_0xB2220000,
 125                 ctl_reg);
 126         writeb(0xda, start_address + ESDCTL_DDR2_MR);
 127         writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
 128
 129         /* OCD mode exit */
 130         writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
 131
 132         /* Set normal mode */
 133         writel(ESDCTL_0x82228080,
 134                 ctl_reg);
 135
 136         dram_wait(0x20000);
 137
 138         /* Do not set delay lines, only for MDDR */
 139 }
 140
 141 static void board_setup_sdram(void)
 142 {
 143         struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
 144
 145         /* Initialize with default values both CSD0/1 */
 146         writel(0x2000, &esdc->esdctl0);
 147         writel(0x2000, &esdc->esdctl1);
 148
 149         board_setup_sdram_bank(CSD0_BASE_ADDR);
 150 }
 151
 152 static void setup_iomux_uart3(void)
 153 {
 154         static const iomux_v3_cfg_t uart3_pads[] = {
 155                 MX35_PAD_RTS2__UART3_RXD_MUX,
 156                 MX35_PAD_CTS2__UART3_TXD_MUX,
 157         };
 158
 159         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 160 }
 161
 162 #define I2C_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
 163
 164 static void setup_iomux_i2c(void)
 165 {
 166         static const iomux_v3_cfg_t i2c_pads[] = {
 167                 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
 168                 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
 169
 170                 NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
 171                 NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
 172         };
 173
 174         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 175 }
 176
 177
 178 static void setup_iomux_spi(void)
 179 {
 180         static const iomux_v3_cfg_t spi_pads[] = {
 181                 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
 182                 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
 183                 MX35_PAD_CSPI1_SS0__CSPI1_SS0,
 184                 MX35_PAD_CSPI1_SS1__CSPI1_SS1,
 185                 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
 186         };
 187
 188         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 189 }
 190
 191 static void setup_iomux_fec(void)
 192 {
 193         static const iomux_v3_cfg_t fec_pads[] = {
 194                 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
 195                 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
 196                 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
 197                 MX35_PAD_FEC_COL__FEC_COL,
 198                 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
 199                 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
 200                 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
 201                 MX35_PAD_FEC_MDC__FEC_MDC,
 202                 MX35_PAD_FEC_MDIO__FEC_MDIO,
 203                 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
 204                 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
 205                 MX35_PAD_FEC_CRS__FEC_CRS,
 206                 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
 207                 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
 208                 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
 209                 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
 210                 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
 211                 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
 212         };
 213
 214         /* setup pins for FEC */
 215         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 216 }
 217
 218 int board_early_init_f(void)
 219 {
 220         struct ccm_regs *ccm =
 221                 (struct ccm_regs *)IMX_CCM_BASE;
 222
 223         /* setup GPIO3_1 to set HighVCore signal */
 224         imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
 225         gpio_direction_output(65, 1);
 226
 227         /* initialize PLL and clock configuration */
 228         writel(CCM_CCMR_CONFIG, &ccm->ccmr);
 229
 230         writel(CCM_MPLL_532_HZ, &ccm->mpctl);
 231         writel(CCM_PPLL_300_HZ, &ccm->ppctl);
 232
 233         /* Set the core to run at 532 Mhz */
 234         writel(0x00001000, &ccm->pdr0);
 235
 236         /* Set-up RAM */
 237         board_setup_sdram();
 238
 239         /* enable clocks */
 240         writel(readl(&ccm->cgr0) |
 241                 MXC_CCM_CGR0_EMI_MASK |
 242                 MXC_CCM_CGR0_EDIO_MASK |
 243                 MXC_CCM_CGR0_EPIT1_MASK,
 244                 &ccm->cgr0);
 245
 246         writel(readl(&ccm->cgr1) |
 247                 MXC_CCM_CGR1_FEC_MASK |
 248                 MXC_CCM_CGR1_GPIO1_MASK |
 249                 MXC_CCM_CGR1_GPIO2_MASK |
 250                 MXC_CCM_CGR1_GPIO3_MASK |
 251                 MXC_CCM_CGR1_I2C1_MASK |
 252                 MXC_CCM_CGR1_I2C2_MASK |
 253                 MXC_CCM_CGR1_I2C3_MASK,
 254                 &ccm->cgr1);
 255
 256         /* Set-up NAND */
 257         __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 258
 259         /* Set pinmux for the required peripherals */
 260         setup_iomux_uart3();
 261         setup_iomux_i2c();
 262         setup_iomux_fec();
 263         setup_iomux_spi();
 264
 265         return 0;
 266 }
 267
 268 int board_init(void)
 269 {
 270         /* address of boot parameters */
 271         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 272
 273         return 0;
 274 }
 275
 276 u32 get_board_rev(void)
 277 {
 278         int rev = 0;
 279
 280         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 281 }
 282
 283 /*
 284  * called prior to booting kernel or by 'fdt boardsetup' command
 285  *
 286  */
 287 int ft_board_setup(void *blob, bd_t *bd)
 288 {
 289         struct node_info nodes[] = {
 290                 { "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
 291                 { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
 292         };
 293
 294         if (getenv("fdt_noauto")) {
 295                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
 296                 return 0;
 297         }
 298
 299         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 300
 301         return 0;
 302 }