board/BuR/brxre1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for B&R BRXRE1 Board
   6  *
   7  * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
   8  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
   9  *
  10  */
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/mem.h>
  22 #include <asm/io.h>
  23 #include <asm/emif.h>
  24 #include <asm/gpio.h>
  25 #include <dm.h>
  26 #include <power/tps65217.h>
  27 #include "../common/bur_common.h"
  28 #include "../common/br_resetc.h"
  29
  30 /* -------------------------------------------------------------------------*/
  31 /* -- defines for used GPIO Hardware -- */
  32 #define ESC_KEY                                 (0 + 19)
  33 #define LCD_PWR                                 (0 + 5)
  34
  35 #define RSTCTRL_FORCE_PWR_NEN                   0x04
  36 #define RSTCTRL_CAN_STB                         0x40
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #if defined(CONFIG_SPL_BUILD)
  41 static const struct ddr_data ddr3_data = {
  42         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  43         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  44         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  45         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  46 };
  47
  48 static const struct cmd_control ddr3_cmd_ctrl_data = {
  49         .cmd0csratio = MT41K256M16HA125E_RATIO,
  50         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  51
  52         .cmd1csratio = MT41K256M16HA125E_RATIO,
  53         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  54
  55         .cmd2csratio = MT41K256M16HA125E_RATIO,
  56         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  57 };
  58
  59 static struct emif_regs ddr3_emif_reg_data = {
  60         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  61         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  62         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  63         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  64         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  65         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  66         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  67 };
  68
  69 static const struct ctrl_ioregs ddr3_ioregs = {
  70         .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  71         .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  72         .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  73         .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  74         .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  75 };
  76
  77 #define OSC     (V_OSCK / 1000000)
  78 const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
  79
  80 void am33xx_spl_board_init(void)
  81 {
  82         int rc;
  83
  84         struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  85         struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  86         /*
  87          * enable additional clocks of modules which are accessed later from
  88          * VxWorks OS
  89          */
  90         u32 *const clk_domains[] = { 0 };
  91
  92         u32 *const clk_modules_xre1specific[] = {
  93                 &cmwkup->wkup_adctscctrl,
  94                 &cmper->spi1clkctrl,
  95                 &cmper->dcan0clkctrl,
  96                 &cmper->dcan1clkctrl,
  97                 &cmper->epwmss0clkctrl,
  98                 &cmper->epwmss1clkctrl,
  99                 &cmper->epwmss2clkctrl,
 100                 &cmper->lcdclkctrl,
 101                 &cmper->lcdcclkstctrl,
 102                 0
 103         };
 104         do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
 105         /* power-OFF LCD-Display */
 106         if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
 107                 printf("cannot request gpio for LCD_PWR!\n");
 108         else if (gpio_direction_output(LCD_PWR, 0) != 0)
 109                 printf("cannot set direction output on LCD_PWR!\n");
 110
 111         /* setup I2C */
 112         enable_i2c_pin_mux();
 113
 114         /* power-ON 3V3 via Resetcontroller */
 115         rc = br_resetc_regset(RSTCTRL_CTRLREG,
 116                               RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
 117         if (rc != 0)
 118                 printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
 119
 120         pmicsetup(0, 0);
 121 }
 122
 123 const struct dpll_params *get_dpll_ddr_params(void)
 124 {
 125         return &dpll_ddr3;
 126 }
 127
 128 void sdram_init(void)
 129 {
 130         config_ddr(400, &ddr3_ioregs,
 131                    &ddr3_data,
 132                    &ddr3_cmd_ctrl_data,
 133                    &ddr3_emif_reg_data, 0);
 134 }
 135 #endif /* CONFIG_SPL_BUILD */
 136 /*
 137  * Basic board specific setup.  Pinmux has been handled already.
 138  */
 139 int board_init(void)
 140 {
 141         /* request common used gpios */
 142         gpio_request(ESC_KEY, "boot-key");
 143
 144         if (power_tps65217_init(0))
 145                 printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
 146
 147         return 0;
 148 }
 149
 150 #ifdef CONFIG_BOARD_LATE_INIT
 151
 152 int board_boot_key(void)
 153 {
 154         return gpio_get_value(ESC_KEY);
 155 }
 156
 157 int board_late_init(void)
 158 {
 159         char othbootargs[128];
 160
 161         br_resetc_bmode();
 162
 163         /* setup othbootargs for bootvx-command (vxWorks bootline) */
 164         snprintf(othbootargs, sizeof(othbootargs),
 165                  "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
 166                  (u32)gd->fb_base - 0x20,
 167                  (u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
 168                  (u32)env_get_ulong("vx_romfsbase", 16, 0),
 169                  (u32)env_get_ulong("vx_romfssize", 16, 0));
 170         env_set("othbootargs", othbootargs);
 171         /*
 172          * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
 173          * expect that vectors are there, original u-boot moves them to _start
 174          */
 175         __asm__("ldr r0,=0x20000");
 176         __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
 177
 178         return 0;
 179 }
 180 #endif /* CONFIG_BOARD_LATE_INIT */