board/BuR/brppt1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for B&R BRPPT1
   6  *
   7  * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
   8  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
   9  *
  10  */
  11
  12 #include <common.h>
  13 #include <bootcount.h>
  14 #include <env.h>
  15 #include <errno.h>
  16 #include <init.h>
  17 #include <spl.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/hardware.h>
  20 #include <asm/arch/omap.h>
  21 #include <asm/arch/ddr_defs.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/io.h>
  27 #include <asm/emif.h>
  28 #include <asm/gpio.h>
  29 #include <i2c.h>
  30 #include <power/tps65217.h>
  31 #include "../common/bur_common.h"
  32 #include <watchdog.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 /* --------------------------------------------------------------------------*/
  37 /* -- defines for GPIO -- */
  38 #define REPSWITCH       (0+20)  /* GPIO0_20 */
  39
  40 #if defined(CONFIG_SPL_BUILD)
  41 /* TODO: check ram-timing ! */
  42 static const struct ddr_data ddr3_data = {
  43         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  44         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  45         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  46         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  47 };
  48
  49 static const struct cmd_control ddr3_cmd_ctrl_data = {
  50         .cmd0csratio = MT41K256M16HA125E_RATIO,
  51         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  52
  53         .cmd1csratio = MT41K256M16HA125E_RATIO,
  54         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  55
  56         .cmd2csratio = MT41K256M16HA125E_RATIO,
  57         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  58 };
  59
  60 static struct emif_regs ddr3_emif_reg_data = {
  61         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  62         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  63         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  64         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  65         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  66         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  67         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  68 };
  69
  70 static const struct ctrl_ioregs ddr3_ioregs = {
  71         .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  72         .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  73         .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  74         .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  75         .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  76 };
  77
  78 #define OSC     (V_OSCK/1000000)
  79 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
  80
  81 void am33xx_spl_board_init(void)
  82 {
  83         int rc;
  84
  85         struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  86         /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
  87         struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  88
  89         /*
  90          * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
  91          * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
  92          * the source of timer6 clk to CLK_M_OSC
  93          */
  94         writel(0x01, &cmdpll->clktimer6clk);
  95
  96         /* enable additional clocks of modules which are accessed later */
  97         u32 *const clk_domains[] = {
  98                 &cmper->lcdcclkstctrl,
  99                 0
 100         };
 101
 102         u32 *const clk_modules_tsspecific[] = {
 103                 &cmper->lcdclkctrl,
 104                 &cmper->timer5clkctrl,
 105                 &cmper->timer6clkctrl,
 106                 0
 107         };
 108         do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
 109
 110         /* setup I2C */
 111         enable_i2c_pin_mux();
 112
 113         pmicsetup(0, 0);
 114
 115         /* peripheral reset */
 116         rc = gpio_request(64 + 29, "GPMC_WAIT1");
 117         if (rc != 0)
 118                 printf("cannot request GPMC_WAIT1 GPIO!\n");
 119         rc = gpio_direction_output(64 + 29, 1);
 120         if (rc != 0)
 121                 printf("cannot set GPMC_WAIT1 GPIO!\n");
 122
 123         rc = gpio_request(64 + 28, "GPMC_WAIT0");
 124         if (rc != 0)
 125                 printf("cannot request GPMC_WAIT0 GPIO!\n");
 126         rc = gpio_direction_output(64 + 28, 1);
 127         if (rc != 0)
 128                 printf("cannot set GPMC_WAIT0 GPIO!\n");
 129
 130 }
 131
 132 const struct dpll_params *get_dpll_ddr_params(void)
 133 {
 134         return &dpll_ddr3;
 135 }
 136
 137 void sdram_init(void)
 138 {
 139         config_ddr(400, &ddr3_ioregs,
 140                    &ddr3_data,
 141                    &ddr3_cmd_ctrl_data,
 142                    &ddr3_emif_reg_data, 0);
 143 }
 144 #endif /* CONFIG_SPL_BUILD */
 145
 146 /* Basic board specific setup.  Pinmux has been handled already. */
 147 int board_init(void)
 148 {
 149 #if defined(CONFIG_HW_WATCHDOG)
 150         hw_watchdog_init();
 151 #endif
 152         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 153 #ifdef CONFIG_MTD_RAW_NAND
 154         gpmc_init();
 155 #endif
 156         return 0;
 157 }
 158
 159 #ifdef CONFIG_BOARD_LATE_INIT
 160 static char *bootmodeascii[16] = {
 161         "BOOT",         "reserved",     "reserved",     "reserved",
 162         "RUN",          "reserved",     "reserved",     "reserved",
 163         "reserved",     "reserved",     "reserved",     "reserved",
 164         "PME",          "reserved",     "reserved",     "DIAG",
 165 };
 166
 167 int board_late_init(void)
 168 {
 169         unsigned char bmode = 0;
 170         ulong bootcount = 0;
 171         int rc;
 172
 173         bootcount = bootcount_load() & 0xF;
 174
 175         rc = gpio_request(REPSWITCH, "REPSWITCH");
 176
 177         if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
 178                 bmode = 12;
 179         else if (bootcount > 0)
 180                 bmode = 0;
 181         else
 182                 bmode = 4;
 183
 184         printf("Mode:  %s\n", bootmodeascii[bmode & 0x0F]);
 185         env_set_ulong("b_mode", bmode);
 186
 187         /* get sure that bootcmd isn't affected by any bootcount value */
 188         env_set_ulong("bootlimit", 0);
 189
 190         return 0;
 191 }
 192 #endif /* CONFIG_BOARD_LATE_INIT */