1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
7 #include <debug_uart.h>
13 #include <asm/cpu_common.h>
14 #include <asm/mrccache.h>
17 #include <asm/processor.h>
19 #include <asm-generic/sections.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 __weak int arch_cpu_init_dm(void)
30 static int set_max_freq(void)
32 if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
34 * Burst Mode has been factory-configured as disabled and is not
35 * available in this physical processor package
37 debug("Burst Mode is factory-disabled\n");
41 /* Enable burst mode */
42 cpu_set_burst_mode(true);
44 /* Enable speed step */
47 /* Set P-State ratio */
48 cpu_set_p_state_to_turbo_ratio();
54 static int x86_spl_init(void)
58 * TODO(sjg@chromium.org): We use this area of RAM for the stack
59 * and global_data in SPL. Once U-Boot starts up and releocates it
60 * is not needed. We could make this a CONFIG option or perhaps
61 * place it immediately below CONFIG_SYS_TEXT_BASE.
63 char *ptr = (char *)0x110000;
65 struct udevice *punit;
69 debug("%s starting\n", __func__);
71 ret = x86_cpu_reinit_f();
73 ret = x86_cpu_init_f();
76 debug("%s: spl_init() failed\n", __func__);
79 ret = arch_cpu_init();
81 debug("%s: arch_cpu_init() failed\n", __func__);
85 ret = arch_cpu_init_dm();
87 debug("%s: arch_cpu_init_dm() failed\n", __func__);
91 preloader_console_init();
93 ret = print_cpuinfo();
95 debug("%s: print_cpuinfo() failed\n", __func__);
101 debug("%s: dram_init() failed\n", __func__);
104 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
105 ret = mrccache_spl_save();
107 debug("%s: Failed to write to mrccache (err=%d)\n",
112 memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
114 /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
115 ret = interrupt_init();
117 debug("%s: interrupt_init() failed\n", __func__);
122 * The stack grows down from ptr. Put the global data at ptr. This
123 * will only be used for SPL. Once SPL loads U-Boot proper it will
124 * set up its own stack.
126 gd->new_gd = (struct global_data *)ptr;
127 memcpy(gd->new_gd, gd, sizeof(*gd));
128 arch_setup_gd(gd->new_gd);
129 gd->start_addr_sp = (ulong)ptr;
131 /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
132 ret = mtrr_add_request(MTRR_TYPE_WRBACK,
133 (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
134 CONFIG_XIP_ROM_SIZE);
136 debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
141 ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
143 debug("Could not find PUNIT (err=%d)\n", ret);
145 ret = set_max_freq();
147 debug("Failed to set CPU frequency (err=%d)\n", ret);
153 void board_init_f(ulong flags)
157 ret = x86_spl_init();
159 debug("Error %d\n", ret);
160 panic("x86_spl_init fail");
163 gd->bd = malloc(sizeof(*gd->bd));
165 printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
170 /* Uninit CAR and jump to board_init_f_r() */
171 board_init_f_r_trampoline(gd->start_addr_sp);
175 void board_init_f_r(void)
178 gd->flags &= ~GD_FLG_SERIAL_READY;
179 debug("cache status %d\n", dcache_status());
183 u32 spl_boot_device(void)
185 return BOOT_DEVICE_SPI_MMAP;
188 int spl_start_uboot(void)
193 void spl_board_announce_boot_device(void)
198 static int spl_board_load_image(struct spl_image_info *spl_image,
199 struct spl_boot_device *bootdev)
201 spl_image->size = CONFIG_SYS_MONITOR_LEN;
202 spl_image->entry_point = CONFIG_SYS_TEXT_BASE;
203 spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
204 spl_image->os = IH_OS_U_BOOT;
205 spl_image->name = "U-Boot";
207 debug("Loading to %lx\n", spl_image->load_addr);
211 SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
213 int spl_spi_load_image(void)
218 #ifdef CONFIG_X86_RUN_64BIT
219 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
223 printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
224 ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
225 debug("ret=%d\n", ret);
230 void spl_board_init(void)
233 preloader_console_init();