1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
12 #include <asm/cmos_layout.h>
13 #include <asm/early_cmos.h>
15 #include <asm/mrccache.h>
17 #include <asm/processor.h>
18 #include <asm/fsp1/fsp_support.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static void *fsp_prepare_mrc_cache(void)
24 struct mrc_data_container *cache;
25 struct mrc_region entry;
28 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
32 cache = mrccache_find_current(&entry);
36 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
37 cache->data, cache->data_size, cache->checksum);
42 int arch_fsp_init(void)
45 int stack = CONFIG_FSP_TEMP_RAM_ADDR;
46 int boot_mode = BOOT_FULL_CONFIG;
47 #ifdef CONFIG_HAVE_ACPI_RESUME
48 int prev_sleep_state = chipset_prev_sleep_state();
49 gd->arch.prev_sleep_state = prev_sleep_state;
52 if (!gd->arch.hob_list) {
53 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
54 nvs = fsp_prepare_mrc_cache();
58 #ifdef CONFIG_HAVE_ACPI_RESUME
59 if (prev_sleep_state == ACPI_S3) {
61 /* If waking from S3 and no cache then */
62 debug("No MRC cache found in S3 resume path\n");
63 post_code(POST_RESUME_FAILURE);
64 /* Clear Sleep Type */
65 chipset_clear_sleep_state();
67 debug("Rebooting..\n");
68 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
69 /* Should not reach here.. */
70 panic("Reboot System");
74 * DM is not available yet at this point, hence call
75 * CMOS access library which does not depend on DM.
77 stack = cmos_read32(CMOS_FSP_STACK_ADDR);
78 boot_mode = BOOT_ON_S3_RESUME;
82 * The first time we enter here, call fsp_init().
83 * Note the execution does not return to this function,
84 * instead it jumps to fsp_continue().
86 fsp_init(stack, boot_mode, nvs);
89 * The second time we enter here, adjust the size of malloc()
90 * pool before relocation. Given gd->malloc_base was adjusted
91 * after the call to board_init_f_init_reserve() in arch/x86/
92 * cpu/start.S, we should fix up gd->malloc_limit here.
94 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;