1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Intel Corporation.
9 /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
10 struct fast_spi_regs {
37 check_member(fast_spi_regs, ptdata, 0xd0);
39 /* Bit definitions for BFPREG (0x00) register */
40 #define SPIBAR_BFPREG_PRB_MASK 0x7fff
41 #define SPIBAR_BFPREG_PRL_SHIFT 16
42 #define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
44 /* PCI configuration registers */
45 #define SPIBAR_BIOS_CONTROL 0xdc
46 #define SPIBAR_BIOS_CONTROL_WPD BIT(0)
47 #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE BIT(1)
48 #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE BIT(2)
49 #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE BIT(3)
50 #define SPIBAR_BIOS_CONTROL_EISS BIT(5)
51 #define SPIBAR_BIOS_CONTROL_BILD BIT(7)
54 * fast_spi_get_bios_mmap() - Get memory map for SPI flash
56 * @pdev: PCI device to use (this is the Fast SPI device)
57 * @map_basep: Returns base memory address for mapped SPI
58 * @map_sizep: Returns size of mapped SPI
59 * @offsetp: Returns start offset of SPI flash where the map works
60 * correctly (offsets before this are not visible)
63 int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
66 int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base);
68 #endif /* ASM_FAST_SPI_H */