1 /* SPDX-License-Identifier: Intel */
3 * Copyright (c) 2016, Intel Corporation. All rights reserved.
4 * Copyright 2019 Google LLC
6 #ifndef __ASM_ARCH_FSP_S_UDP_H
7 #define __ASM_ARCH_FSP_S_UDP_H
10 #include <asm/fsp2/fsp_api.h>
13 * struct fsp_s_config - FSP-S configuration
15 * Note that struct fsp_upd_header preceeds this and is 32 bytes long. The
16 * hex offsets mentioned in this file are relative to the start of the header,
17 * the same convention used in Intel's APL FSP header file.
19 struct __packed fsp_s_config {
21 u8 active_processor_cores;
26 u8 proc_trace_mem_size;
34 u8 c_state_auto_demotion;
35 u8 c_state_un_demotion;
39 u8 pkg_c_state_demotion;
40 u8 pkg_c_state_un_demotion;
42 u8 hda_verb_table_entry_num;
43 u32 hda_verb_table_ptr;
53 u8 graphics_freq_modify;
55 u8 graphics_video_freq;
58 u8 unsolicited_attack_override;
62 u8 unit_level_clock_gating;
69 u8 enable_render_standby;
72 u32 graphics_config_ptr;
78 u8 pei_graphics_peim_init;
79 u8 write_protection_enable[5];
80 u8 read_protection_enable[5];
81 u16 protected_range_limit[5];
82 u16 protected_range_base[5];
84 u8 clk_gating_pgcb_clk_trunk;
86 u8 clk_gating_sb_clk_trunk;
87 u8 clk_gating_sb_clk_partition;
90 u8 clk_gating_reg_access;
92 u8 clk_gating_partition;
99 u8 hd_audio_io_buffer_ownership;
100 u8 hd_audio_io_buffer_voltage;
102 u8 hd_audio_link_frequency;
103 u8 hd_audio_i_disp_link_frequency;
104 u8 hd_audio_i_disp_link_tmode;
105 u8 dsp_endpoint_dmic;
106 u8 dsp_endpoint_bluetooth;
107 u8 dsp_endpoint_i2s_skp;
108 u8 dsp_endpoint_i2s_hp;
109 u8 audio_ctl_pwr_gate;
110 u8 audio_dsp_pwr_gate;
113 u8 hd_audio_pwr_gate;
114 u8 hd_audio_clk_gate;
117 u32 dsp_feature_mask;
118 u32 dsp_pp_module_mask;
119 u8 bios_cfg_lock_down;
123 u8 hpet_device_number;
124 u8 hpet_function_number;
125 u8 io_apic_bdf_valid;
126 u8 io_apic_bus_number;
129 u8 io_apic_device_number;
130 u8 io_apic_function_number;
131 u8 io_apic_entry24_119;
133 u8 io_apic_range_select;
138 u8 bios_lock_sw_smi_number;
140 u8 unused_upd_space0[1];
141 u8 i2c_clk_gate_cfg[8];
142 u8 hsuart_clk_gate_cfg[4];
143 u8 spi_clk_gate_cfg[3];
163 u32 uart2_kernel_debug_base_address;
166 u8 pcie_clock_gating_disabled;
167 u8 pcie_root_port8xh_decode;
168 u8 pcie8xh_decode_port_index;
169 u8 pcie_root_port_peer_memory_write_enable;
170 u8 pcie_aspm_sw_smi_number;
171 u8 unused_upd_space1[1];
172 u8 pcie_root_port_en[6];
174 u8 pcie_rp_slot_implemented[6];
175 u8 pcie_rp_hot_plug[6];
176 u8 pcie_rp_pm_sci[6];
177 u8 pcie_rp_ext_sync[6];
178 u8 pcie_rp_transmitter_half_swing[6];
181 u8 pcie_rp_acs_enabled[6];
182 u8 pcie_rp_clk_req_supported[6];
183 u8 pcie_rp_clk_req_number[6];
184 u8 pcie_rp_clk_req_detect[6];
185 u8 advanced_error_reporting[6];
187 u8 unsupported_request_report[6];
188 u8 fatal_error_report[6];
191 u8 no_fatal_error_report[6];
192 u8 correctable_error_report[6];
193 u8 system_error_on_fatal_error[6];
194 u8 system_error_on_non_fatal_error[6];
195 u8 system_error_on_correctable_error[6];
197 u8 physical_slot_number[6];
198 u8 pcie_rp_completion_timeout[6];
203 u8 pcie_rp_l1_substates[6];
204 u8 pcie_rp_ltr_enable[6];
205 u8 pcie_rp_ltr_config_lock[6];
210 u8 timer8254_clk_setting;
213 u8 sata_salp_support;
214 u8 sata_pwr_opt_enable;
215 u8 e_sata_speed_limit;
217 u8 unused_upd_space2[1];
218 u8 sata_ports_enable[2];
219 u8 sata_ports_dev_slp[2];
220 u8 sata_ports_hot_plug[2];
221 u8 sata_ports_interlock_sw[2];
224 u8 sata_ports_external[2];
225 u8 sata_ports_spin_up[2];
226 u8 sata_ports_solid_state_drive[2];
227 u8 sata_ports_enable_dito_config[2];
228 u8 sata_ports_dm_val[2];
229 u8 unused_upd_space3[2];
230 u16 sata_ports_dito_val[2];
233 u16 sub_system_vendor_id;
239 u8 e_mmc_host_max_speed;
245 u8 start_frame_pulse;
250 u8 unused_upd_space4;
251 u16 num_rsvd_smbus_addresses;
252 u8 rsvd_smbus_address_table[128];
253 u8 disable_compliance_mode;
256 u8 unused_upd_space5[1];
257 u8 port_usb20_enable[8];
260 u8 port_us20b_over_current_pin[8];
262 u8 hsic_support_enable;
263 u8 port_usb30_enable[6];
266 u8 port_us30b_over_current_pin[6];
267 u8 ssic_port_enable[2];
268 u16 dlane_pwr_gating;
270 u8 lock_down_global_smi;
271 u16 reset_wait_timer;
277 u16 dynamic_power_gating;
278 u16 pcie_rp_ltr_max_snoop_latency[6];
281 u8 pcie_rp_snoop_latency_override_mode[6];
282 u8 unused_upd_space6[2];
283 u16 pcie_rp_snoop_latency_override_value[6];
284 u8 pcie_rp_snoop_latency_override_multiplier[6];
287 u16 pcie_rp_ltr_max_non_snoop_latency[6];
288 u8 pcie_rp_non_snoop_latency_override_mode[6];
289 u8 tco_timer_halt_lock;
290 u8 pwr_btn_override_period;
293 u16 pcie_rp_non_snoop_latency_override_value[6];
294 u8 pcie_rp_non_snoop_latency_override_multiplier[6];
295 u8 pcie_rp_slot_power_limit_scale[6];
296 u8 pcie_rp_slot_power_limit_value[6];
297 u8 disable_native_power_button;
298 u8 power_butter_debounce_mode;
301 u32 sdio_tx_cmd_cntl;
302 u32 sdio_tx_data_cntl1;
303 u32 sdio_tx_data_cntl2;
304 u32 sdio_rx_cmd_data_cntl1;
307 u32 sdio_rx_cmd_data_cntl2;
308 u32 sdcard_tx_cmd_cntl;
309 u32 sdcard_tx_data_cntl1;
310 u32 sdcard_tx_data_cntl2;
313 u32 sdcard_rx_cmd_data_cntl1;
314 u32 sdcard_rx_strobe_cntl;
315 u32 sdcard_rx_cmd_data_cntl2;
316 u32 emmc_tx_cmd_cntl;
319 u32 emmc_tx_data_cntl1;
320 u32 emmc_tx_data_cntl2;
321 u32 emmc_rx_cmd_data_cntl1;
322 u32 emmc_rx_strobe_cntl;
325 u32 emmc_rx_cmd_data_cntl2;
326 u32 emmc_master_sw_cntl;
327 u8 pcie_rp_selectable_deemphasis[6];
328 u8 monitor_mwait_enable;
329 u8 hd_audio_dsp_uaa_compliance;
335 u8 sata_ports_disable_dynamic_pg[2];
338 u8 unused_upd_space7[4];
339 u8 port_usb20_per_port_tx_pe_half[8];
342 u8 port_usb20_per_port_pe_txi_set[8];
343 u8 port_usb20_per_port_txi_set[8];
346 u8 port_usb20_hs_skew_sel[8];
347 u8 port_usb20_i_usb_tx_emphasis_en[8];
350 u8 port_usb20_per_port_rxi_set[8];
351 u8 port_usb20_hs_npre_drv_sel[8];
354 u8 reserved_fsps_upd[16];
357 /** struct fsps_upd - FSP-S Configuration */
358 struct __packed fsps_upd {
359 struct fsp_upd_header header;
360 struct fsp_s_config config;
361 u8 unused_upd_space2[46];
366 #define PROC_TRACE_MEM_SIZE_DISABLE 0xff
368 #define BOOT_P_STATE_HFM 0
369 #define BOOT_P_STATE_LFM 1
371 #define PKG_C_STATE_LIMIT_C0_C1 0
372 #define PKG_C_STATE_LIMIT_C2 1
373 #define PKG_C_STATE_LIMIT_C3 2
374 #define PKG_C_STATE_LIMIT_C6 3
375 #define PKG_C_STATE_LIMIT_C7 4
376 #define PKG_C_STATE_LIMIT_C7S 5
377 #define PKG_C_STATE_LIMIT_C8 6
378 #define PKG_C_STATE_LIMIT_C9 7
379 #define PKG_C_STATE_LIMIT_C10 8
380 #define PKG_C_STATE_LIMIT_CMAX 9
381 #define PKG_C_STATE_LIMIT_CPU_DEFAULT 254
382 #define PKG_C_STATE_LIMIT_AUTO 255
384 #define C_STATE_AUTO_DEMOTION_DISABLE_C1_C3 0
385 #define C_STATE_AUTO_DEMOTION_ENABLE_C3_C6_C7_TO_C1 1
386 #define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C3 2
387 #define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C1_C3 3
389 #define C_STATE_UN_DEMOTION_DISABLE_C1_C3 0
390 #define C_STATE_UN_DEMOTION_ENABLE_C1 1
391 #define C_STATE_UN_DEMOTION_ENABLE_C3 2
392 #define C_STATE_UN_DEMOTION_ENABLE_C1_C3 3
394 #define MAX_CORE_C_STATE_UNLIMITED 0
395 #define MAX_CORE_C_STATE_C1 1
396 #define MAX_CORE_C_STATE_C3 2
397 #define MAX_CORE_C_STATE_C6 3
398 #define MAX_CORE_C_STATE_C7 4
399 #define MAX_CORE_C_STATE_C8 5
400 #define MAX_CORE_C_STATE_C9 6
401 #define MAX_CORE_C_STATE_C10 7
402 #define MAX_CORE_C_STATE_CCX 8
404 #define IPU_ACPI_MODE_DISABLE 0
405 #define IPU_ACPI_MODE_IGFX_CHILD_DEVICE 1
406 #define IPU_ACPI_MODE_ACPI_DEVICE 1
408 #define CD_CLOCK_FREQ_144MHZ 0
409 #define CD_CLOCK_FREQ_288MHZ 1
410 #define CD_CLOCK_FREQ_384MHZ 2
411 #define CD_CLOCK_FREQ_576MHZ 3
412 #define CD_CLOCK_FREQ_624MHZ 4
414 #define HDA_IO_BUFFER_OWNERSHIP_HDA_ALL_IO 0
415 #define HDA_IO_BUFFER_OWNERSHIP_HDA_I2S_SPLIT 1
416 #define HDA_IO_BUFFER_OWNERSHIP_I2S_ALL_IO 2
418 #define HDA_IO_BUFFER_VOLTAGE_3V3 0
419 #define HDA_IO_BUFFER_VOLTAGE_1V8 1
421 #define HDA_VC_TYPE_VC0 0
422 #define HDA_VC_TYPE_VC1 1
424 #define HDA_LINK_FREQ_6MHZ 0
425 #define HDA_LINK_FREQ_12MHZ 1
426 #define HDA_LINK_FREQ_24MHZ 2
427 #define HDA_LINK_FREQ_48MHZ 3
428 #define HDA_LINK_FREQ_96MHZ 4
429 #define HDA_LINK_FREQ_INVALID 5
431 #define HDA_I_DISP_LINK_FREQ_6MHZ 0
432 #define HDA_I_DISP_LINK_FREQ_12MHZ 1
433 #define HDA_I_DISP_LINK_FREQ_24MHZ 2
434 #define HDA_I_DISP_LINK_FREQ_48MHZ 3
435 #define HDA_I_DISP_LINK_FREQ_96MHZ 4
436 #define HDA_I_DISP_LINK_FREQ_INVALID 5
438 #define HDA_I_DISP_LINK_T_MODE_2T 0
439 #define HDA_I_DISP_LINK_T_MODE_1T 1
441 #define HDA_DISP_DMIC_DISABLE 0
442 #define HDA_DISP_DMIC_2CH_ARRAY 1
443 #define HDA_DISP_DMIC_4CH_ARRAY 2
445 #define HDA_CSE_MEM_TRANSFERS_VC0 0
446 #define HDA_CSE_MEM_TRANSFERS_VC2 1
448 #define HDA_HOST_MEM_TRANSFERS_VC0 0
449 #define HDA_HOST_MEM_TRANSFERS_VC2 1
451 #define HDA_DSP_FEATURE_MASK_WOV 0x1
452 #define HDA_DSP_FEATURE_MASK_BT_SIDEBAND 0x2
453 #define HDA_DSP_FEATURE_MASK_CODEC_VAD 0x4
454 #define HDA_DSP_FEATURE_MASK_BT_INTEL_HFP 0x20
455 #define HDA_DSP_FEATURE_MASK_BT_INTEL_A2DP 0x40
456 #define HDA_DSP_FEATURE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80
458 #define HDA_DSP_PP_MODULE_MASK_WOV 0x1
459 #define HDA_DSP_PP_MODULE_MASK_BT_SIDEBAND 0x2
460 #define HDA_DSP_PP_MODULE_MASK_CODEC_VAD 0x4
461 #define HDA_DSP_PP_MODULE_MASK_BT_INTEL_HFP 0x20
462 #define HDA_DSP_PP_MODULE_MASK_BT_INTEL_A2DP 0x40
463 #define HDA_DSP_PP_MODULE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80
465 #define I2CX_ENABLE_DISABLED 0
466 #define I2CX_ENABLE_PCI_MODE 1
467 #define I2CX_ENABLE_ACPI_MODE 2
469 #define HSUARTX_ENABLE_DISABLED 0
470 #define HSUARTX_ENABLE_PCI_MODE 1
471 #define HSUARTX_ENABLE_ACPI_MODE 2
473 #define SPIX_ENABLE_DISABLED 0
474 #define SPIX_ENABLE_PCI_MODE 1
475 #define SPIX_ENABLE_ACPI_MODE 2
477 #define PCIE_RP_SPEED_AUTO 0
478 #define PCIE_RP_SPEED_GEN1 1
479 #define PCIE_RP_SPEED_GEN2 2
480 #define PCIE_RP_SPEED_GEN3 3
482 #define PCIE_RP_ASPM_DISABLE 0
483 #define PCIE_RP_ASPM_L0S 1
484 #define PCIE_RP_ASPM_L1 2
485 #define PCIE_RP_ASPM_L0S_L1 3
486 #define PCIE_RP_ASPM_AUTO 4
488 #define PCIE_RP_L1_SUBSTATES_DISABLE 0
489 #define PCIE_RP_L1_SUBSTATES_L1_1 1
490 #define PCIE_RP_L1_SUBSTATES_L1_2 2
491 #define PCIE_RP_L1_SUBSTATES_L1_1_L1_2 3
493 #define SATA_MODE_AHCI 0
494 #define SATA_MODE_RAID 1
496 #define SATA_SPEED_LIMIT_SC_SATA_SPEED 0
497 #define SATA_SPEED_LIMIT_1_5GBS 1
498 #define SATA_SPEED_LIMIT_3GBS 2
499 #define SATA_SPEED_LIMIT_6GBS 3
501 #define SATA_PORT_SOLID_STATE_DRIVE_HARD_DISK_DRIVE 0
502 #define SATA_PORT_SOLID_STATE_DRIVE_SOLID_STATE_DRIVE 1
504 #define CRID_SETTING_DISABLE 0
505 #define CRID_SETTING_CRID_1 1
506 #define CRID_SETTING_CRID_2 2
507 #define CRID_SETTING_CRID_3 3
509 #define RESET_SELECT_WARM_RESET 0x6
510 #define RESET_SELECT_COLD_RESET 0xe
512 #define EMMC_HOST_SPEED_MAX_HS400 0
513 #define EMMC_HOST_SPEED_MAX_HS200 1
514 #define EMMC_HOST_SPEED_MAX_DDR50 2
516 #define SERIAL_IRQ_MODE_QUIET_MODE 0
517 #define SERIAL_IRQ_MODE_CONTINUOUS_MODE 1
519 #define START_FRAME_PULSE_WIDTH_SCSFPW4CLK 0
520 #define START_FRAME_PULSE_WIDTH_SCSFPW6CLK 1
521 #define START_FRAME_PULSE_WIDTH_SCSFPW8CLK 1
523 #define USB30_MODE_DISABLE 0
524 #define USB30_MODE_ENABLE 1
525 #define USB30_MODE_AUTO 2
527 #define USB_OTG_DISABLE 0
528 #define USB_OTG_PCI_MODE 1
529 #define USB_OTG_ACPI_MODE 2
531 #define SSIC_RATE_A_SERIES 1
532 #define SSIC_RATE_B_SERIES 2
534 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0
535 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1
536 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2
538 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0
539 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1
540 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2
541 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3
542 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4
543 #define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5
545 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0
546 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1
547 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2
549 #define PWR_BTN_OVERRIDE_PERIOD_4S 0
550 #define PWR_BTN_OVERRIDE_PERIOD_6S 1
551 #define PWR_BTN_OVERRIDE_PERIOD_8S 2
552 #define PWR_BTN_OVERRIDE_PERIOD_10S 3
553 #define PWR_BTN_OVERRIDE_PERIOD_12S 4
554 #define PWR_BTN_OVERRIDE_PERIOD_14S 5
556 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0
557 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1
558 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2
559 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3
560 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4
561 #define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5
563 #define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0
564 #define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1