arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h

   1 /* SPDX-License-Identifier: Intel */
   2 /*
   3  * Copyright (c) 2019, Intel Corporation. All rights reserved.
   4  * Copyright 2019 Google LLC
   5  */
   6
   7 #ifndef __ASM_ARCH_FSP_M_UDP_H
   8 #define __ASM_ARCH_FSP_M_UDP_H
   9
  10 #ifndef __ASSEMBLY__
  11 #include <asm/fsp2/fsp_api.h>
  12
  13 #define FSP_DRAM_CHANNELS       4
  14
  15 struct __packed fspm_arch_upd {
  16         u8      revision;
  17         u8      reserved[3];
  18         void    *nvs_buffer_ptr;
  19         void    *stack_base;
  20         u32     stack_size;
  21         u32     boot_loader_tolum_size;
  22         u32     boot_mode;
  23         u8      reserved1[8];
  24 };
  25
  26 struct __packed fsp_ram_channel {
  27         u8      rank_enable;
  28         u8      device_width;
  29         u8      dram_density;
  30         u8      option;
  31         u8      odt_config;
  32         u8      tristate_clk1;
  33         u8      mode2_n;
  34         u8      odt_levels;
  35 };
  36
  37 struct __packed fsp_m_config {
  38         u32     serial_debug_port_address;
  39         u8      serial_debug_port_type;
  40         u8      serial_debug_port_device;
  41         u8      serial_debug_port_stride_size;
  42         u8      mrc_fast_boot;
  43         u8      igd;
  44         u8      igd_dvmt50_pre_alloc;
  45         u8      igd_aperture_size;
  46         u8      gtt_size;
  47         u8      primary_video_adaptor;
  48         u8      package;
  49         u8      profile;
  50         u8      memory_down;
  51
  52         u8      ddr3_l_page_size;
  53         u8      ddr3_lasr;
  54         u8      scrambler_support;
  55         u8      interleaved_mode;
  56         u16     channel_hash_mask;
  57         u16     slice_hash_mask;
  58         u8      channels_slices_enable;
  59         u8      min_ref_rate2x_enable;
  60         u8      dual_rank_support_enable;
  61         u8      rmt_mode;
  62         u16     memory_size_limit;
  63         u16     low_memory_max_value;
  64
  65         u16     high_memory_max_value;
  66         u8      disable_fast_boot;
  67         u8      dimm0_spd_address;
  68         u8      dimm1_spd_address;
  69         struct fsp_ram_channel chan[FSP_DRAM_CHANNELS];
  70         u8      rmt_check_run;
  71         u16     rmt_margin_check_scale_high_threshold;
  72         u8      ch_bit_swizzling[FSP_DRAM_CHANNELS][32];
  73         u32     msg_level_mask;
  74         u8      unused_upd_space0[4];
  75
  76         u8      pre_mem_gpio_table_pin_num[4];
  77         u32     pre_mem_gpio_table_ptr;
  78         u8      pre_mem_gpio_table_entry_num;
  79         u8      enhance_port8xh_decoding;
  80         u8      spd_write_enable;
  81         u8      mrc_data_saving;
  82         u32     oem_loading_base;
  83
  84         u8      oem_file_name[16];
  85
  86         void    *mrc_boot_data_ptr;
  87         u8      e_mmc_trace_len;
  88         u8      skip_cse_rbp;
  89         u8      npk_en;
  90         u8      fw_trace_en;
  91         u8      fw_trace_destination;
  92         u8      recover_dump;
  93         u8      msc0_wrap;
  94         u8      msc1_wrap;
  95         u32     msc0_size;
  96
  97         u32     msc1_size;
  98         u8      pti_mode;
  99         u8      pti_training;
 100         u8      pti_speed;
 101         u8      punit_mlvl;
 102
 103         u8      pmc_mlvl;
 104         u8      sw_trace_en;
 105         u8      periodic_retraining_disable;
 106         u8      enable_reset_system;
 107
 108         u8      enable_s3_heci2;
 109         u8      unused_upd_space1[3];
 110
 111         void    *variable_nvs_buffer_ptr;
 112         u8      reserved_fspm_upd[12];
 113 };
 114
 115 /** FSP-M UPD Configuration */
 116 struct __packed fspm_upd {
 117         struct fsp_upd_header header;
 118         struct fspm_arch_upd arch;
 119         struct fsp_m_config config;
 120         u8 unused_upd_space2[158];
 121         u16 upd_terminator;
 122 };
 123 #endif
 124
 125 #define SERIAL_DEBUG_PORT_TYPE_NONE 0
 126 #define SERIAL_DEBUG_PORT_TYPE_IO 1
 127 #define SERIAL_DEBUG_PORT_TYPE_MMIO 2
 128
 129 #define SERIAL_DEBUG_PORT_DEVICE_UART0 0
 130 #define SERIAL_DEBUG_PORT_DEVICE_UART1 1
 131 #define SERIAL_DEBUG_PORT_DEVICE_UART2 2
 132 #define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3
 133
 134 #define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0
 135 #define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2
 136
 137 #define IGD_DVMT_50_PRE_ALLOC_64M 0x02
 138 #define IGD_DVMT_50_PRE_ALLOC_96M 0x03
 139 #define IGD_DVMT_50_PRE_ALLOC_128M 0x04
 140 #define IGD_DVMT_50_PRE_ALLOC_160M 0x05
 141 #define IGD_DVMT_50_PRE_ALLOC_192M 0x06
 142 #define IGD_DVMT_50_PRE_ALLOC_224M 0x07
 143 #define IGD_DVMT_50_PRE_ALLOC_256M 0x08
 144 #define IGD_DVMT_50_PRE_ALLOC_288M 0x09
 145 #define IGD_DVMT_50_PRE_ALLOC_320M 0x0a
 146 #define IGD_DVMT_50_PRE_ALLOC_352M 0x0b
 147 #define IGD_DVMT_50_PRE_ALLOC_384M 0x0c
 148 #define IGD_DVMT_50_PRE_ALLOC_416M 0x0d
 149 #define IGD_DVMT_50_PRE_ALLOC_448M 0x0e
 150 #define IGD_DVMT_50_PRE_ALLOC_480M 0x0f
 151 #define IGD_DVMT_50_PRE_ALLOC_512M 0x10
 152
 153 #define IGD_APERTURE_SIZE_128M 0x1
 154 #define IGD_APERTURE_SIZE_256M 0x2
 155 #define IGD_APERTURE_SIZE_512M 0x3
 156
 157 #define GTT_SIZE_2M 1
 158 #define GTT_SIZE_4M 2
 159 #define GTT_SIZE_8M 3
 160
 161 #define PRIMARY_VIDEO_ADAPTER_AUTO 0
 162 #define PRIMARY_VIDEO_ADAPTER_IGD 2
 163 #define PRIMARY_VIDEO_ADAPTER_PCI 3
 164
 165 #define PACKAGE_SODIMM 0
 166 #define PACKAGE_BGA 1
 167 #define PACKAGE_BGA_MIRRORED 2
 168 #define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3
 169
 170 #define PROFILE_WIO2_800_7_8_8 0x1
 171 #define PROFILE_WIO2_1066_9_10_10 0x2
 172 #define PROFILE_LPDDR3_1066_8_10_10 0x3
 173 #define PROFILE_LPDDR3_1333_10_12_12 0x4
 174 #define PROFILE_LPDDR3_1600_12_15_15 0x5
 175 #define PROFILE_LPDDR3_1866_14_17_17 0x6
 176 #define PROFILE_LPDDR3_2133_16_20_20 0x7
 177 #define PROFILE_LPDDR4_1066_10_10_10 0x8
 178 #define PROFILE_LPDDR4_1600_14_15_15 0x9
 179 #define PROFILE_LPDDR4_2133_20_20_20 0xa
 180 #define PROFILE_LPDDR4_2400_24_22_22 0xb
 181 #define PROFILE_LPDDR4_2666_24_24_24 0xc
 182 #define PROFILE_LPDDR4_2933_28_27_27 0xd
 183 #define PROFILE_LPDDR4_3200_28_29_29 0xe
 184 #define PROFILE_DDR3_1066_6_6_6 0xf
 185 #define PROFILE_DDR3_1066_7_7_7 0x10
 186 #define PROFILE_DDR3_1066_8_8_8 0x11
 187 #define PROFILE_DDR3_1333_7_7_7 0x12
 188 #define PROFILE_DDR3_1333_8_8_8 0x13
 189 #define PROFILE_DDR3_1333_9_9_9 0x14
 190 #define PROFILE_DDR3_1333_10_10_10 0x15
 191 #define PROFILE_DDR3_1600_8_8_8 0x16
 192 #define PROFILE_DDR3_1600_9_9_9 0x17
 193 #define PROFILE_DDR3_1600_10_10_10 0x18
 194 #define PROFILE_DDR3_1600_11_11_11 0x19
 195 #define PROFILE_DDR3_1866_10_10_10 0x1a
 196 #define PROFILE_DDR3_1866_11_11_11 0x1b
 197 #define PROFILE_DDR3_1866_12_12_12 0x1c
 198 #define PROFILE_DDR3_1866_13_13_13 0x1d
 199 #define PROFILE_DDR3_2133_11_11_11 0x1e
 200 #define PROFILE_DDR3_2133_12_12_12 0x1f
 201 #define PROFILE_DDR3_2133_13_13_13 0x20
 202 #define PROFILE_DDR3_2133_14_14_14 0x21
 203 #define PROFILE_DDR4_1333_10_10_10 0x22
 204 #define PROFILE_DDR4_1600_10_10_10 0x23
 205 #define PROFILE_DDR4_1600_11_11_11 0x24
 206 #define PROFILE_DDR4_1600_12_12_12 0x25
 207 #define PROFILE_DDR4_1866_12_12_12 0x26
 208 #define PROFILE_DDR4_1866_13_13_13 0x27
 209 #define PROFILE_DDR4_1866_14_14_14 0x28
 210 #define PROFILE_DDR4_2133_14_14_14 0x29
 211 #define PROFILE_DDR4_2133_15_15_15 0x2a
 212 #define PROFILE_DDR4_2133_16_16_16 0x2b
 213 #define PROFILE_DDR4_2400_15_15_15 0x2c
 214 #define PROFILE_DDR4_2400_16_16_16 0x2d
 215 #define PROFILE_DDR4_2400_17_17_17 0x2e
 216 #define PROFILE_DDR4_2400_18_18_18 0x2f
 217
 218 #define MEMORY_DOWN_NO 0
 219 #define MEMORY_DOWN_YES 1
 220 #define MEMORY_DOWN_MD_SODIMM 2
 221 #define MEMORY_DOWN_LPDDR4 3
 222
 223 #define DDR3L_PAGE_SIZE_1KB 1
 224 #define DDR3L_PAGE_SIZE_2KB 2
 225
 226 #define INTERLEAVED_MODE_DISABLE 0
 227 #define INTERLEAVED_MODE_ENABLE 2
 228
 229 #define RMT_MODE_DISABLE 0
 230 #define RMT_MODE_ENABLE 3
 231
 232 #define CHX_DEVICE_WIDTH_X8 0
 233 #define CHX_DEVICE_WIDTH_X16 1
 234 #define CHX_DEVICE_WIDTH_X32 2
 235 #define CHX_DEVICE_WIDTH_X64 3
 236
 237 #define CHX_DEVICE_DENSITY_4GB 0
 238 #define CHX_DEVICE_DENSITY_6GB 1
 239 #define CHX_DEVICE_DENSITY_8GB 2
 240 #define CHX_DEVICE_DENSITY_12GB 3
 241 #define CHX_DEVICE_DENSITY_16GB 4
 242 #define CHX_DEVICE_DENSITY_2GB 5
 243
 244 #define CHX_OPTION_RANK_INTERLEAVING 0x1
 245 #define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2
 246 #define CHX_OPTION_CH1_CLK_DISABLE 0x4
 247 #define CHX_OPTION_ADDRESS_MAP_2KB 0x10
 248
 249 #define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1
 250 #define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2
 251 #define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10
 252
 253 #define CHX_MODE2N_AUTO 0
 254 #define CHX_MODE2N_FORCE 1
 255
 256 #define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0
 257 #define CHX_ODT_LEVELS_HELD_HIGH 0x1
 258
 259 #define NPK_EN_DISABLE 0
 260 #define NPK_EN_ENABLE 1
 261 #define NPK_EN_DEBUGGER 2
 262 #define NPK_EN_AUTO 3
 263
 264 #define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1
 265 #define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2
 266 #define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3
 267 #define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4
 268
 269 #define MSC_X_WRAP_0 0
 270 #define MSC_X_WRAP_1 1
 271
 272 #define MSC_X_SIZE_0M 0
 273 #define MSC_X_SIZE_1M 1
 274 #define MSC_X_SIZE_8M 2
 275 #define MSC_X_SIZE_64M 3
 276 #define MSC_X_SIZE_128M 4
 277 #define MSC_X_SIZE_256M 5
 278 #define MSC_X_SIZE_512M 6
 279 #define MSC_X_SIZE_1GB 7
 280
 281 #define PTI_MODE_0 0
 282 #define PTI_MODE_x4 1
 283 #define PTI_MODE_x8 2
 284 #define PTI_MODE_x12 3
 285 #define PTI_MODE_x16 4
 286
 287 #define PTI_SPEED_FULL 0
 288 #define PTI_SPEED_HALF 1
 289 #define PTI_SPEED_QUARTER 2
 290
 291 #endif