arch/x86/dts/chromebook_coral.dts

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /dts-v1/;
   3
   4 #include <dt-bindings/gpio/x86-gpio.h>
   5
   6 /include/ "skeleton.dtsi"
   7 /include/ "keyboard.dtsi"
   8 /include/ "reset.dtsi"
   9 /include/ "rtc.dtsi"
  10 /include/ "tsc_timer.dtsi"
  11
  12 #ifdef CONFIG_CHROMEOS
  13 #include "chromeos-x86.dtsi"
  14 #include "flashmap-x86-ro.dtsi"
  15 #include "flashmap-16mb-rw.dtsi"
  16 #endif
  17
  18 #include <asm/intel_pinctrl_defs.h>
  19 #include <asm/arch-apollolake/cpu.h>
  20 #include <asm/arch-apollolake/gpio.h>
  21 #include <asm/arch-apollolake/iomap.h>
  22 #include <asm/arch-apollolake/pm.h>
  23 #include <dt-bindings/clock/intel-clock.h>
  24
  25 / {
  26         model = "Google Coral";
  27         compatible = "google,coral", "intel,apollolake";
  28
  29         aliases {
  30                 cros-ec0 = &cros_ec;
  31                 fsp = &fsp_s;
  32                 spi0 = &spi;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41         };
  42
  43         config {
  44                silent_console = <0>;
  45         };
  46
  47         chosen {
  48                 stdout-path = &serial;
  49         };
  50
  51         clk: clock {
  52                 compatible = "intel,apl-clk";
  53                 #clock-cells = <1>;
  54         };
  55
  56         cpus {
  57                 u-boot,dm-pre-reloc;
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu@0 {
  62                         u-boot,dm-pre-reloc;
  63                         device_type = "cpu";
  64                         compatible = "intel,apl-cpu";
  65                         reg = <0>;
  66                         intel,apic-id = <0>;
  67                 };
  68
  69                 cpu@1 {
  70                         device_type = "cpu";
  71                         compatible = "intel,apl-cpu";
  72                         reg = <1>;
  73                         intel,apic-id = <2>;
  74                 };
  75
  76                 cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "intel,apl-cpu";
  79                         reg = <2>;
  80                         intel,apic-id = <4>;
  81                 };
  82
  83                 cpu@3 {
  84                         device_type = "cpu";
  85                         compatible = "intel,apl-cpu";
  86                         reg = <3>;
  87                         intel,apic-id = <6>;
  88                 };
  89
  90         };
  91
  92         acpi_gpe: general-purpose-events {
  93                 reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
  94                 compatible = "intel,acpi-gpe";
  95                 interrupt-controller;
  96                 #interrupt-cells = <2>;
  97         };
  98
  99         keyboard {
 100                 intel,duplicate-por;
 101         };
 102
 103         pci {
 104                 compatible = "pci-x86";
 105                 #address-cells = <3>;
 106                 #size-cells = <2>;
 107                 u-boot,dm-pre-reloc;
 108                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 109                         0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
 110                         0x01000000 0x0 0x1000 0x1000 0 0xefff>;
 111                 u-boot,skip-auto-config-until-reloc;
 112
 113                 host_bridge: host-bridge@0,0 {
 114                         u-boot,dm-pre-reloc;
 115                         reg = <0x00000000 0 0 0 0>;
 116                         compatible = "intel,apl-hostbridge";
 117                         pciex-region-size = <0x10000000>;
 118                         /*
 119                          * Parameters used by the FSP-S binary blob. This is
 120                          * really unfortunate since these parameters mostly
 121                          * relate to drivers but we need them in one place. We
 122                          * could put them in the driver nodes easily, but then
 123                          * would have to scan each node to find them. So just
 124                          * dump them here for now.
 125                          */
 126                         fsp_s: fsp-s {
 127                         };
 128                 };
 129
 130                 punit@0,1 {
 131                         u-boot,dm-pre-reloc;
 132                         reg = <0x00000800 0 0 0 0>;
 133                         compatible = "intel,apl-punit";
 134                 };
 135
 136                 p2sb: p2sb@d,0 {
 137                         u-boot,dm-pre-reloc;
 138                         reg = <0x02006810 0 0 0 0>;
 139                         compatible = "intel,p2sb";
 140                         early-regs = <IOMAP_P2SB_BAR 0x100000>;
 141
 142                         n {
 143                                 compatible = "intel,apl-pinctrl";
 144                                 u-boot,dm-pre-reloc;
 145                                 intel,p2sb-port-id = <PID_GPIO_N>;
 146                                 gpio_n: gpio-n {
 147                                         compatible = "intel,gpio";
 148                                         u-boot,dm-pre-reloc;
 149                                         gpio-controller;
 150                                         #gpio-cells = <2>;
 151                                 };
 152                         };
 153
 154                         nw {
 155                                 u-boot,dm-pre-reloc;
 156                                 compatible = "intel,apl-pinctrl";
 157                                 intel,p2sb-port-id = <PID_GPIO_NW>;
 158                                 #gpio-cells = <2>;
 159                                 gpio_nw: gpio-nw {
 160                                         compatible = "intel,gpio";
 161                                         u-boot,dm-pre-reloc;
 162                                         gpio-controller;
 163                                         #gpio-cells = <2>;
 164                                 };
 165                         };
 166
 167                         w {
 168                                 u-boot,dm-pre-reloc;
 169                                 compatible = "intel,apl-pinctrl";
 170                                 intel,p2sb-port-id = <PID_GPIO_W>;
 171                                 #gpio-cells = <2>;
 172                                 gpio_w: gpio-w {
 173                                         compatible = "intel,gpio";
 174                                         u-boot,dm-pre-reloc;
 175                                         gpio-controller;
 176                                         #gpio-cells = <2>;
 177                                 };
 178                         };
 179
 180                         sw {
 181                                 u-boot,dm-pre-reloc;
 182                                 compatible = "intel,apl-pinctrl";
 183                                 intel,p2sb-port-id = <PID_GPIO_SW>;
 184                                 #gpio-cells = <2>;
 185                                 gpio_sw: gpio-sw {
 186                                         compatible = "intel,gpio";
 187                                         u-boot,dm-pre-reloc;
 188                                         gpio-controller;
 189                                         #gpio-cells = <2>;
 190                                 };
 191                         };
 192
 193                         itss {
 194                                 u-boot,dm-pre-reloc;
 195                                 compatible = "intel,itss";
 196                                 intel,p2sb-port-id = <PID_ITSS>;
 197                                 intel,pmc-routes = <
 198                                         PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
 199                                         PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
 200                                         PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
 201                                         PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
 202                                         PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
 203                                         PMC_GPE_N_31_0 GPIO_GPE_N_31_0
 204                                         PMC_GPE_N_63_32 GPIO_GPE_N_63_32
 205                                         PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
 206                         };
 207                 };
 208
 209                 pmc@d,1 {
 210                         u-boot,dm-pre-reloc;
 211                         reg = <0x6900 0 0 0 0>;
 212
 213                         /*
 214                          * Values for BAR0, BAR2 and ACPI_BASE for when PCI
 215                          * auto-configure is not available
 216                          */
 217                         early-regs = <0xfe042000 0x2000
 218                                 0xfe044000 0x2000
 219                                 IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
 220                         compatible = "intel,apl-pmc";
 221                         gpe0-dwx-mask = <0xf>;
 222                         gpe0-dwx-shift-base = <4>;
 223
 224                         /*
 225                          * GPE configuration
 226                          * Note that GPE events called out in ASL code rely on
 227                          * this route, i.e., if this route changes then the
 228                          * affected GPE * offset bits also need to be changed.
 229                          * This sets the PMC register GPE_CFG fields.
 230                          */
 231                         gpe0-dw = <PMC_GPE_N_31_0
 232                                 PMC_GPE_N_63_32
 233                                 PMC_GPE_SW_31_0>;
 234                         gpe0-sts = <0x20>;
 235                         gpe0-en = <0x30>;
 236                 };
 237
 238                 spi: fast-spi@d,2 {
 239                         u-boot,dm-pre-reloc;
 240                         reg = <0x02006a10 0 0 0 0>;
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         compatible = "intel,fast-spi";
 244                         early-regs = <IOMAP_SPI_BASE 0x1000>;
 245                         intel,hardware-seq = <1>;
 246
 247                         fwstore_spi: spi-flash@0 {
 248                                 #size-cells = <1>;
 249                                 #address-cells = <1>;
 250                                 u-boot,dm-pre-reloc;
 251                                 reg = <0>;
 252                                 compatible = "winbond,w25q128fw",
 253                                          "jedec,spi-nor";
 254                                 rw-mrc-cache {
 255                                         label = "rw-mrc-cache";
 256                                         reg = <0x008e0000 0x00010000>;
 257                                         u-boot,dm-pre-reloc;
 258                                 };
 259                                 rw-var-mrc-cache {
 260                                         label = "rw-mrc-cache";
 261                                         reg = <0x008f0000 0x0001000>;
 262                                         u-boot,dm-pre-reloc;
 263                                 };
 264                         };
 265                 };
 266
 267                 i2c_0: i2c2@16,0 {
 268                         compatible = "intel,apl-i2c";
 269                         reg = <0x0200b010 0 0 0 0>;
 270                         clocks = <&clk CLK_I2C>;
 271                         i2c-scl-rising-time-ns = <104>;
 272                         i2c-scl-falling-time-ns = <52>;
 273                 };
 274
 275                 i2c_1: i2c2@16,1 {
 276                         compatible = "intel,apl-i2c";
 277                         reg = <0x0200b110 0 0 0 0>;
 278                         clocks = <&clk CLK_I2C>;
 279                         status = "disabled";
 280                 };
 281
 282                 i2c_2: i2c2@16,2 {
 283                         compatible = "intel,apl-i2c";
 284                         reg = <0x0200b210 0 0 0 0>;
 285                         #address-cells = <1>;
 286                         #size-cells = <0>;
 287                         clock-frequency = <400000>;
 288                         clocks = <&clk CLK_I2C>;
 289                         i2c-scl-rising-time-ns = <57>;
 290                         i2c-scl-falling-time-ns = <28>;
 291                         tpm@50 {
 292                                 reg = <0x50>;
 293                                 compatible = "google,cr50";
 294                                 u-boot,i2c-offset-len = <0>;
 295                                 ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
 296                                 interrupts-extended = <&acpi_gpe 0x3c 0>;
 297                         };
 298                 };
 299
 300                 i2c_3: i2c2@16,3 {
 301                         compatible = "intel,apl-i2c";
 302                         reg = <0x0200b110 0 0 0 0>;
 303                         clocks = <&clk CLK_I2C>;
 304                         i2c-scl-rising-time-ns = <76>;
 305                         i2c-scl-falling-time-ns = <164>;
 306                 };
 307
 308                 i2c_4: i2c2@17,0 {
 309                         compatible = "intel,apl-i2c";
 310                         reg = <0x0200b110 0 0 0 0>;
 311                         clocks = <&clk CLK_I2C>;
 312                         i2c-sda-hold-time-ns = <350>;
 313                         i2c-scl-rising-time-ns = <114>;
 314                         i2c-scl-falling-time-ns = <164>;
 315                 };
 316
 317                 i2c_5: i2c2@17,1 {
 318                         compatible = "intel,apl-i2c";
 319                         reg = <0x0200b110 0 0 0 0>;
 320                         clocks = <&clk CLK_I2C>;
 321                         i2c-scl-rising-time-ns = <76>;
 322                         i2c-scl-falling-time-ns = <164>;
 323                 };
 324
 325                 i2c_6: i2c2@17,2 {
 326                         compatible = "intel,apl-i2c";
 327                         reg = <0x0200b110 0 0 0 0>;
 328                         clocks = <&clk CLK_I2C>;
 329                         status = "disabled";
 330                 };
 331
 332                 i2c_7: i2c2@17,3 {
 333                         compatible = "intel,apl-i2c";
 334                         reg = <0x0200b110 0 0 0 0>;
 335                         clocks = <&clk CLK_I2C>;
 336                         status = "disabled";
 337                 };
 338
 339                 serial: serial@18,2 {
 340                         reg = <0x0200c210 0 0 0 0>;
 341                         u-boot,dm-pre-reloc;
 342                         compatible = "intel,apl-ns16550";
 343                         early-regs = <0xde000000 0x20>;
 344                         reg-shift = <2>;
 345                         clock-frequency = <1843200>;
 346                         current-speed = <115200>;
 347                 };
 348
 349                 pch: pch@1f,0 {
 350                         reg = <0x0000f800 0 0 0 0>;
 351                         compatible = "intel,apl-pch";
 352                         u-boot,dm-pre-reloc;
 353                         #address-cells = <1>;
 354                         #size-cells = <1>;
 355
 356                         lpc {
 357                                 compatible = "intel,apl-lpc";
 358                                 #address-cells = <1>;
 359                                 #size-cells = <0>;
 360                                 u-boot,dm-pre-reloc;
 361                                 cros_ec: cros-ec {
 362                                         u-boot,dm-pre-reloc;
 363                                         compatible = "google,cros-ec-lpc";
 364                                         reg = <0x204 1 0x200 1 0x880 0x80>;
 365
 366                                         /*
 367                                          * Describes the flash memory within
 368                                          * the EC
 369                                          */
 370                                         #address-cells = <1>;
 371                                         #size-cells = <1>;
 372                                         flash@8000000 {
 373                                                 reg = <0x08000000 0x20000>;
 374                                                 erase-value = <0xff>;
 375                                         };
 376                                 };
 377                         };
 378                 };
 379         };
 380
 381 };
 382
 383 &host_bridge {
 384         /*
 385          * PL1 override 12000 mW: the energy calculation is wrong with the
 386          * current VR solution. Experiments show that SoC TDP max (6W) can be
 387          * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
 388          */
 389         tdp-pl-override-mw = <12000 15000>;
 390
 391         early-pads = <
 392                 /* These two are for the debug UART */
 393                 GPIO_46 /* UART2 RX */
 394                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 395                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 396
 397                 GPIO_47 /* UART2 TX */
 398                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 399                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 400
 401                 GPIO_75 /* I2S1_BCLK -- PCH_WP */
 402                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
 403                         (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
 404
 405                 /* I2C2 - TPM  */
 406                 GPIO_128 /* LPSS_I2C2_SDA */
 407                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 408                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 409                 GPIO_129 /* LPSS_I2C2_SCL */
 410                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 411                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 412                 GPIO_28 /* TPM IRQ */
 413                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 414                                 PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
 415                                 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
 416                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
 417
 418                 /*
 419                  * WLAN_PE_RST - default to deasserted just in case FSP
 420                  * misbehaves
 421                  */
 422                 GPIO_122  /* SIO_SPI_2_RXD */
 423                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 424                                 PAD_CFG0_RX_DISABLE | 0)
 425                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 426
 427                 /* LPC */
 428                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 429                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 430                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 431                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 432                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 433                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 434                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 435                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 436                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 437                 >;
 438
 439         lpddr4-swizzle = /bits/ 8 <
 440                 /* LP4_PHYS_CH0A */
 441
 442                 /* DQA[0:7] pins of LPDDR4 module */
 443                 6 7 5 4 3 1 0 2
 444                 /* DQA[8:15] pins of LPDDR4 module */
 445                 12 10 11 13 14 8 9 15
 446                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 447                 16 22 23 20 18 17 19 21
 448                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 449                 30 28 29 25 24 26 27 31
 450
 451                 /* LP4_PHYS_CH0B */
 452                 /* DQA[0:7] pins of LPDDR4 module */
 453                 7 3 5 2 6 0 1 4
 454                 /* DQA[8:15] pins of LPDDR4 module */
 455                  9 14 12 13 10 11 8 15
 456                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 457                 20 22 23 16 19 17 18 21
 458                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 459                 28 24 26 27 29 30 31 25
 460
 461                 /* LP4_PHYS_CH1A */
 462
 463                 /* DQA[0:7] pins of LPDDR4 module */
 464                 2 1 6 7 5 4 3 0
 465                 /* DQA[8:15] pins of LPDDR4 module */
 466                 11 10 8 9 12 15 13 14
 467                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 468                 17 23 19 16 21 22 20 18
 469                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 470                 31 29 26 25 28 27 24 30
 471
 472                 /* LP4_PHYS_CH1B */
 473
 474                 /* DQA[0:7] pins of LPDDR4 module */
 475                 4 3 7 5 6 1 0 2
 476                 /* DQA[8:15] pins of LPDDR4 module */
 477                 15 9 8 11 14 13 12 10
 478                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 479                 20 23 22 21 18 19 16 17
 480                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 481                 25 28 30 31 26 27 24 29>;
 482 };
 483
 484 &fsp_s {
 485         u-boot,dm-pre-proper;
 486
 487         /* Disable unused clkreq of PCIe root ports */
 488         pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */
 489                 CLKREQ_DISABLED
 490                 CLKREQ_DISABLED
 491                 CLKREQ_DISABLED
 492                 CLKREQ_DISABLED
 493                 CLKREQ_DISABLED>;
 494
 495         /*
 496          * GPIO for PERST_0
 497          * If the Board has PERST_0 signal, assign the GPIO
 498          * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
 499          *
 500          * This are not used yet, so comment them out for now.
 501          *
 502          * prt0-gpio = <GPIO_122>;
 503          *
 504          * GPIO for SD card detect
 505          * sdcard-cd-gpio = <GPIO_177>;
 506          */
 507
 508         /*
 509          * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
 510          * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
 511          *
 512          * EMMC TX DATA Delay 1
 513          * Refer to EDS-Vol2-22.3
 514          * [14:8] steps of delay for HS400, each 125ps
 515          * [6:0] steps of delay for SDR104/HS200, each 125ps
 516
 517         /*
 518          * EMMC TX DATA Delay 2
 519          * Refer to EDS-Vol2-22.3.
 520          * [30:24] steps of delay for SDR50, each 125ps
 521          * [22:16] steps of delay for DDR50, each 125ps
 522          * [14:8] steps of delay for SDR25/HS50, each 125ps
 523          * [6:0] steps of delay for SDR12, each 125ps
 524          */
 525
 526         /*
 527          * EMMC RX CMD/DATA Delay 1
 528          * Refer to EDS-Vol2-22.3.
 529          * [30:24] steps of delay for SDR50, each 125ps
 530          * [22:16] steps of delay for DDR50, each 125ps
 531          * [14:8] steps of delay for SDR25/HS50, each 125ps
 532          * [6:0] steps of delay for SDR12, each 125ps
 533          */
 534
 535         /*
 536          * EMMC RX CMD/DATA Delay 2
 537          * Refer to EDS-Vol2-22.3.
 538          * [17:16] stands for Rx Clock before Output Buffer
 539          * [14:8] steps of delay for Auto Tuning Mode, each 125ps
 540          * [6:0] steps of delay for HS200, each 125ps
 541          */
 542         emmc = <0x0c16 0x28162828 0x00181717 0x10008>;
 543
 544         /* Enable DPTF */
 545         dptf-enable;
 546
 547         /* Enable Audio Clock and Power gating */
 548         hdaudio-clk-gate-enable;
 549         hdaudio-pwr-gate-enable;
 550         hdaudio-bios-config-lockdown;
 551
 552         /* Enable lpss s0ix */
 553         lpss-s0ix-enable;
 554
 555         /*
 556          * TODO(sjg@chromium.org): Move this to the I2C nodes
 557          * Intel Common SoC Config
 558          *+-------------------+---------------------------+
 559          *| Field             |  Value                    |
 560          *+-------------------+---------------------------+
 561          *| I2C0              | Audio                     |
 562          *| I2C2              | TPM                       |
 563          *| I2C3              | Touchscreen               |
 564          *| I2C4              | Trackpad                  |
 565          *| I2C5              | Digitizer                 |
 566          *+-------------------+---------------------------+
 567          *
 568         common_soc_config" = "{
 569                 .i2c[0] = {
 570                         .speed = I2C_SPEED_FAST,
 571                         .rise-time-ns = 104,
 572                         .fall-time-ns = 52,
 573                 },
 574                 .i2c[2] = {
 575                         .early_init = 1,
 576                         .speed = I2C_SPEED_FAST,
 577                         .rise-time-ns = 57,
 578                         .fall-time-ns = 28,
 579                 },
 580                 .i2c[3] = {
 581                         .speed = I2C_SPEED_FAST,
 582                         .rise-time-ns = 76,
 583                         .fall-time-ns = 164,
 584                 },
 585                 .i2c[4] = {
 586                         .speed = I2C_SPEED_FAST,
 587                         .rise-time-ns = 114,
 588                         .fall-time-ns = 164,
 589                         .data_hold_time_ns = 350,
 590                 },
 591                 .i2c[5] = {
 592                         .speed = I2C_SPEED_FAST,
 593                         .rise-time-ns = 152,
 594                         .fall-time-ns = 30,
 595                 },
 596         }"
 597         */
 598
 599         /* Minimum SLP S3 assertion width 28ms */
 600         slp-s3-assertion-width-usecs = <28000>;
 601
 602         pads = <
 603                 /* PCIE_WAKE[0:3]_N */
 604                 PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
 605                 PAD_CFG_GPI(GPIO_206, UP_20K, DEEP)      /* Unused */
 606                 PAD_CFG_GPI(GPIO_207, UP_20K, DEEP)      /* Unused */
 607                 PAD_CFG_GPI(GPIO_208, UP_20K, DEEP)      /* Unused */
 608
 609                 /* EMMC interface */
 610                 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
 611                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
 612                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
 613                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
 614                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
 615                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
 616                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
 617                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
 618                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
 619                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
 620                 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
 621
 622                 /* SDIO -- unused */
 623                 PAD_CFG_GPI(GPIO_166, UP_20K, DEEP)      /* SDIO_CLK */
 624                 PAD_CFG_GPI(GPIO_167, UP_20K, DEEP)      /* SDIO_D0 */
 625                 /* Configure SDIO to enable power gating */
 626                 PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
 627                 PAD_CFG_GPI(GPIO_169, UP_20K, DEEP)      /* SDIO_D2 */
 628                 PAD_CFG_GPI(GPIO_170, UP_20K, DEEP)      /* SDIO_D3 */
 629                 PAD_CFG_GPI(GPIO_171, UP_20K, DEEP)      /* SDIO_CMD */
 630
 631                 /* SDCARD */
 632                 /* Pull down clock by 20K */
 633                 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
 634                 PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
 635                 PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
 636                 PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
 637                 PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
 638                 /* Card detect is active LOW with external pull up */
 639                 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
 640                 PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
 641                 /* CLK feedback, internal signal, needs 20K pull down */
 642                 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
 643                 /* No h/w write proect for uSD cards, pull down by 20K */
 644                 PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
 645                 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
 646                 PAD_CFG_GPO(GPIO_183, 0, DEEP)           /* SDIO_PWR_DOWN_N */
 647
 648                 /* SMBus -- unused */
 649                 PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP)    /* SMB_ALERT _N */
 650                 PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP)       /* SMB_CLK */
 651                 PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP)      /* SMB_DATA */
 652
 653                 /* LPC */
 654                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 655                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 656                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 657                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 658                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 659                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 660                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 661                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 662                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 663
 664                 /* I2C0 - Audio */
 665                 PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
 666                 PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
 667
 668                 /* I2C1 - NFC with external pulls */
 669                 PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
 670                 PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
 671
 672                 /* I2C2 - TPM  */
 673                 PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
 674                 PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
 675
 676                 /* I2C3 - touch */
 677                 PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
 678                 PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
 679
 680                 /* I2C4 - trackpad */
 681                 /* LPSS_I2C4_SDA */
 682                 PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
 683                 /* LPSS_I2C4_SCL */
 684                 PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
 685
 686                 /* I2C5 -- pen with external pulls  */
 687                 PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
 688                 PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
 689
 690                 /* I2C6-7 -- unused */
 691                 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP)      /* LPSS_I2C6_SDA */
 692                 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP)      /* LPSS_I2C6_SCL */
 693                 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP)      /* LPSS_I2C7_SDA */
 694                 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP)      /* LPSS_I2C7_SCL */
 695
 696                 /* Audio Amp - I2S6 */
 697                 PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
 698                 PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
 699                 PAD_CFG_GPI(GPIO_148, UP_20K, DEEP)      /* ISH_GPIO_2 - unused */
 700                 PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
 701
 702                 /* NFC Reset */
 703                 PAD_CFG_GPO(GPIO_150, 1, DEEP)           /* ISH_GPIO_4 */
 704
 705                 PAD_CFG_GPI(GPIO_151, UP_20K, DEEP)      /* ISH_GPIO_5 - unused */
 706
 707                 /* Touch enable */
 708                 PAD_CFG_GPO(GPIO_152, 1, DEEP)           /* ISH_GPIO_6 */
 709
 710                 PAD_CFG_GPI(GPIO_153, UP_20K, DEEP)      /* ISH_GPIO_7 - unused */
 711                 PAD_CFG_GPI(GPIO_154, UP_20K, DEEP)      /* ISH_GPIO_8 - unused */
 712                 PAD_CFG_GPI(GPIO_155, UP_20K, DEEP)      /* ISH_GPIO_9 - unused */
 713
 714                 /* PCIE_CLKREQ[0:3]_N */
 715                 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1)    /* WLAN with external pull */
 716                 PAD_CFG_GPI(GPIO_210, UP_20K, DEEP)      /* unused */
 717                 PAD_CFG_GPI(GPIO_211, UP_20K, DEEP)      /* unused */
 718                 PAD_CFG_GPI(GPIO_212, UP_20K, DEEP)      /* unused */
 719
 720                 /* OSC_CLK_OUT_[0:4] -- unused */
 721                 PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
 722                 PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
 723                 PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
 724                 PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
 725                 PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
 726
 727                 /* PMU Signals */
 728                 PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
 729                 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
 730                 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
 731                 PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
 732                 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
 733                 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
 734                 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
 735                 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
 736                 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
 737                 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP)         /* EN_PP3300_EMMC */
 738                 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
 739                 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
 740
 741                 /* DDI[0:1] SDA and SCL -- unused */
 742                 PAD_CFG_GPI(GPIO_187, UP_20K, DEEP)      /* HV_DDI0_DDC_SDA */
 743                 PAD_CFG_GPI(GPIO_188, UP_20K, DEEP)      /* HV_DDI0_DDC_SCL */
 744                 PAD_CFG_GPI(GPIO_189, UP_20K, DEEP)      /* HV_DDI1_DDC_SDA */
 745                 PAD_CFG_GPI(GPIO_190, UP_20K, DEEP)      /* HV_DDI1_DDC_SCL */
 746
 747                 /* MIPI I2C -- unused */
 748                 PAD_CFG_GPI(GPIO_191, UP_20K, DEEP)      /* MIPI_I2C_SDA */
 749                 PAD_CFG_GPI(GPIO_192, UP_20K, DEEP)      /* MIPI_I2C_SCL */
 750
 751                 /* Panel 0 control */
 752                 PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
 753                 PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
 754                 PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
 755
 756                 /* Panel 1 control -- unused */
 757                 PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
 758                 PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
 759                 PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
 760
 761                 /* Hot plug detect */
 762                 PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
 763                 PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
 764
 765                 /* MDSI signals -- unused */
 766                 PAD_CFG_GPI(GPIO_201, UP_20K, DEEP)      /* MDSI_A_TE */
 767                 PAD_CFG_GPI(GPIO_202, UP_20K, DEEP)      /* MDSI_A_TE */
 768
 769                 /* USB overcurrent pins */
 770                 PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
 771                 PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
 772
 773                 /* PMC SPI -- almost entirely unused */
 774                 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
 775                 PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
 776                 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
 777                 PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
 778                 PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
 779                 PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
 780
 781                 /* PMIC Signals Unused signals related to an old PMIC interface */
 782                 PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
 783                 PAD_CFG_GPI(GPIO_213, NONE, DEEP)        /* unused external pull */
 784                 PAD_CFG_GPI(GPIO_214, UP_20K, DEEP)      /* unused */
 785                 PAD_CFG_GPI(GPIO_215, UP_20K, DEEP)      /* unused */
 786                 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
 787                 PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP)    /* unused */
 788                 PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
 789                 PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
 790                 PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
 791
 792                 /* I2S1 -- largely unused */
 793                 PAD_CFG_GPI(GPIO_74, UP_20K, DEEP)      /* I2S1_MCLK */
 794                 PAD_CFG_GPI(GPIO_75, UP_20K, DEEP)      /* I2S1_BCLK -- PCH_WP */
 795                 PAD_CFG_GPO(GPIO_76, 0, DEEP)           /* I2S1_WS_SYNC -- SPK_PA_EN */
 796                 PAD_CFG_GPI(GPIO_77, UP_20K, DEEP)      /* I2S1_SDI */
 797                 PAD_CFG_GPO(GPIO_78, 1, DEEP)           /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
 798
 799                 /* DMIC or I2S4 */
 800                 /* AVS_DMIC_CLK_A1 */
 801                 PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
 802                 PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
 803                 PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1)  /* AVS_DMIC_DATA_1 */
 804                 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP)       /* unused -- strap */
 805                 PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
 806
 807                 /* I2S2 -- Headset amp */
 808                 PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1)   /* AVS_I2S2_MCLK */
 809                 PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1)   /* AVS_I2S2_BCLK */
 810                 PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1)   /* AVS_I2S2_SW_SYNC */
 811                 PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDI */
 812                 PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDO */
 813
 814                 /* I2S3 -- largely unused */
 815                 PAD_CFG_GPI(GPIO_89, UP_20K, DEEP)       /* unused */
 816                 PAD_CFG_GPI(GPIO_90, UP_20K, DEEP)       /* GPS_HOST_WAKE */
 817                 PAD_CFG_GPO(GPIO_91, 1, DEEP)            /* GPS_EN */
 818                 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP)       /* unused -- strap */
 819
 820                 /* Fast SPI */
 821                 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
 822                 PAD_CFG_GPI(GPIO_98, UP_20K, DEEP)                              /* FST_SPI_CS1_B -- unused */
 823                 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
 824                 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_MISO_IO1 */
 825                 PAD_CFG_GPI(GPIO_101, NONE, DEEP)                               /* FST_IO2 -- MEM_CONFIG0 */
 826                 PAD_CFG_GPI(GPIO_102, NONE, DEEP)                               /* FST_IO3 -- MEM_CONFIG1 */
 827                 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_CLK */
 828                 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
 829                 PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE)        /* FST_SPI_CS2_N */
 830
 831                 /* SIO_SPI_0 - Used for FP */
 832                 PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_CLK */
 833                 PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_FS0 */
 834                 PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_RXD */
 835                 PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_TXD */
 836
 837                 /* SIO_SPI_1 -- largely unused */
 838                 PAD_CFG_GPI(GPIO_111, UP_20K, DEEP)      /* SIO_SPI_1_CLK */
 839                 PAD_CFG_GPI(GPIO_112, UP_20K, DEEP)      /* SIO_SPI_1_FS0 */
 840                 PAD_CFG_GPI(GPIO_113, UP_20K, DEEP)      /* SIO_SPI_1_FS1 */
 841                 /* Headset interrupt */
 842                 PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
 843                 PAD_CFG_GPI(GPIO_117, UP_20K, DEEP)      /* SIO_SPI_1_TXD */
 844
 845                 /* SIO_SPI_2 -- unused */
 846                 PAD_CFG_GPI(GPIO_118, UP_20K, DEEP)      /* SIO_SPI_2_CLK */
 847                 PAD_CFG_GPI(GPIO_119, UP_20K, DEEP)      /* SIO_SPI_2_FS0 */
 848                 PAD_CFG_GPI(GPIO_120, UP_20K, DEEP)      /* SIO_SPI_2_FS1 */
 849                 PAD_CFG_GPI(GPIO_121, UP_20K, DEEP)      /* SIO_SPI_2_FS2 */
 850                 /* WLAN_PE_RST - default to deasserted */
 851                 PAD_CFG_GPO(GPIO_122, 0, DEEP)           /* SIO_SPI_2_RXD */
 852                 PAD_CFG_GPI(GPIO_123, UP_20K, DEEP)      /* SIO_SPI_2_TXD */
 853
 854                 /* Debug tracing */
 855                 PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
 856                 PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
 857                 PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
 858                 PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL)        /* FP_INT */
 859                 PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
 860                 PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
 861                 PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
 862                 PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
 863                 PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
 864
 865                 PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
 866                 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP)       /* Board phase enforcement */
 867                 PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI  */
 868                 PAD_CFG_GPI(GPIO_12, UP_20K, DEEP)       /* unused */
 869                 PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
 870                 PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
 871                 PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE)    /* TRACKPAD_INT_1V8_ODL */
 872                 PAD_CFG_GPI(GPIO_16, UP_20K, DEEP)       /* unused */
 873                 PAD_CFG_GPI(GPIO_17, UP_20K, DEEP)       /* 1 vs 4 DMIC config */
 874                 PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
 875                 PAD_CFG_GPI(GPIO_19, UP_20K, DEEP)       /* unused */
 876                 PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
 877                 PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
 878                 PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
 879                 PAD_CFG_GPI(GPIO_23, UP_20K, DEEP)       /* unused */
 880                 PAD_CFG_GPI(GPIO_24, NONE, DEEP)         /* PEN_PDCT_ODL */
 881                 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP)       /* unused */
 882                 PAD_CFG_GPI(GPIO_26, UP_20K, DEEP)       /* unused */
 883                 PAD_CFG_GPI(GPIO_27, UP_20K, DEEP)       /* unused */
 884                 PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
 885                 PAD_CFG_GPO(GPIO_29, 1, DEEP)            /* FP reset */
 886                 PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
 887                 PAD_CFG_GPO(GPIO_31, 0, DEEP)            /* NFC FW DL */
 888                 PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5)     /* SUS_CLK2 */
 889                 PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
 890                 PAD_CFG_GPI(GPIO_34, UP_20K, DEEP)       /* unused */
 891                 PAD_CFG_GPO(GPIO_35, 0, DEEP)            /* PEN_RESET - active high */
 892                 PAD_CFG_GPO(GPIO_36, 0, DEEP)            /* touch reset */
 893                 PAD_CFG_GPI(GPIO_37, UP_20K, DEEP)       /* unused */
 894
 895                 /* LPSS_UART[0:2] */
 896                 PAD_CFG_GPI(GPIO_38, NONE, DEEP)         /* LPSS_UART0_RXD - MEM_CONFIG2*/
 897                 /* Next 2 are straps */
 898                 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP)       /* LPSS_UART0_TXD - unused */
 899                 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP)       /* LPSS_UART0_RTS - unused */
 900                 PAD_CFG_GPI(GPIO_41, NONE, DEEP)         /* LPSS_UART0_CTS - EC_IN_RW */
 901                 PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1)   /* LPSS_UART1_RXD */
 902                 PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1)   /* LPSS_UART1_TXD */
 903                 PAD_CFG_GPO(GPIO_44, 1, DEEP)    /* GPS_RST_ODL */
 904                 PAD_CFG_GPI(GPIO_45, NONE, DEEP)         /* LPSS_UART1_CTS - MEM_CONFIG3 */
 905                 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1)   /* LPSS_UART2_RXD */
 906                 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
 907                 PAD_CFG_GPI(GPIO_48, UP_20K, DEEP)       /* LPSS_UART2_RTS - unused */
 908                 PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
 909
 910                 /* Camera interface -- completely unused */
 911                 PAD_CFG_GPI(GPIO_62, UP_20K, DEEP)       /* GP_CAMERASB00 */
 912                 PAD_CFG_GPI(GPIO_63, UP_20K, DEEP)       /* GP_CAMERASB01 */
 913                 PAD_CFG_GPI(GPIO_64, UP_20K, DEEP)       /* GP_CAMERASB02 */
 914                 PAD_CFG_GPI(GPIO_65, UP_20K, DEEP)       /* GP_CAMERASB03 */
 915                 PAD_CFG_GPI(GPIO_66, UP_20K, DEEP)       /* GP_CAMERASB04 */
 916                 PAD_CFG_GPI(GPIO_67, UP_20K, DEEP)       /* GP_CAMERASB05 */
 917                 PAD_CFG_GPI(GPIO_68, UP_20K, DEEP)       /* GP_CAMERASB06 */
 918                 PAD_CFG_GPI(GPIO_69, UP_20K, DEEP)       /* GP_CAMERASB07 */
 919                 PAD_CFG_GPI(GPIO_70, UP_20K, DEEP)       /* GP_CAMERASB08 */
 920                 PAD_CFG_GPI(GPIO_71, UP_20K, DEEP)       /* GP_CAMERASB09 */
 921                 PAD_CFG_GPI(GPIO_72, UP_20K, DEEP)       /* GP_CAMERASB10 */
 922                 PAD_CFG_GPI(GPIO_73, UP_20K, DEEP)       /* GP_CAMERASB11 */
 923         >;
 924 };