arch/x86/dts/chromebook_coral.dts

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /dts-v1/;
   3
   4 #include <dt-bindings/gpio/x86-gpio.h>
   5
   6 /include/ "skeleton.dtsi"
   7 /include/ "keyboard.dtsi"
   8 /include/ "reset.dtsi"
   9 /include/ "rtc.dtsi"
  10 /include/ "tsc_timer.dtsi"
  11
  12 #ifdef CONFIG_CHROMEOS
  13 #include "chromeos-x86.dtsi"
  14 #include "flashmap-x86-ro.dtsi"
  15 #include "flashmap-16mb-rw.dtsi"
  16 #endif
  17
  18 #include <asm/intel_pinctrl_defs.h>
  19 #include <asm/arch-apollolake/cpu.h>
  20 #include <asm/arch-apollolake/gpio.h>
  21 #include <asm/arch-apollolake/iomap.h>
  22 #include <asm/arch-apollolake/pm.h>
  23 #include <dt-bindings/clock/intel-clock.h>
  24 #include <asm/arch-apollolake/fsp/fsp_m_upd.h>
  25
  26 / {
  27         model = "Google Coral";
  28         compatible = "google,coral", "intel,apollolake";
  29
  30         aliases {
  31                 cros-ec0 = &cros_ec;
  32                 fsp = &fsp_s;
  33                 spi0 = &spi;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &i2c_4;
  39                 i2c5 = &i2c_5;
  40                 i2c6 = &i2c_6;
  41                 i2c7 = &i2c_7;
  42         };
  43
  44         config {
  45                silent_console = <0>;
  46         };
  47
  48         chosen {
  49                 stdout-path = &serial;
  50         };
  51
  52         clk: clock {
  53                 compatible = "intel,apl-clk";
  54                 #clock-cells = <1>;
  55         };
  56
  57         cpus {
  58                 u-boot,dm-pre-reloc;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 cpu@0 {
  63                         u-boot,dm-pre-reloc;
  64                         device_type = "cpu";
  65                         compatible = "intel,apl-cpu";
  66                         reg = <0>;
  67                         intel,apic-id = <0>;
  68                 };
  69
  70                 cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "intel,apl-cpu";
  73                         reg = <1>;
  74                         intel,apic-id = <2>;
  75                 };
  76
  77                 cpu@2 {
  78                         device_type = "cpu";
  79                         compatible = "intel,apl-cpu";
  80                         reg = <2>;
  81                         intel,apic-id = <4>;
  82                 };
  83
  84                 cpu@3 {
  85                         device_type = "cpu";
  86                         compatible = "intel,apl-cpu";
  87                         reg = <3>;
  88                         intel,apic-id = <6>;
  89                 };
  90
  91         };
  92
  93         acpi_gpe: general-purpose-events {
  94                 reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
  95                 compatible = "intel,acpi-gpe";
  96                 interrupt-controller;
  97                 #interrupt-cells = <2>;
  98         };
  99
 100         keyboard {
 101                 intel,duplicate-por;
 102         };
 103
 104         pci {
 105                 compatible = "pci-x86";
 106                 #address-cells = <3>;
 107                 #size-cells = <2>;
 108                 u-boot,dm-pre-reloc;
 109                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 110                         0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
 111                         0x01000000 0x0 0x1000 0x1000 0 0xefff>;
 112                 u-boot,skip-auto-config-until-reloc;
 113
 114                 host_bridge: host-bridge@0,0 {
 115                         u-boot,dm-pre-reloc;
 116                         reg = <0x00000000 0 0 0 0>;
 117                         compatible = "intel,apl-hostbridge";
 118                         pciex-region-size = <0x10000000>;
 119                         /*
 120                          * Parameters used by the FSP-S binary blob. This is
 121                          * really unfortunate since these parameters mostly
 122                          * relate to drivers but we need them in one place. We
 123                          * could put them in the driver nodes easily, but then
 124                          * would have to scan each node to find them. So just
 125                          * dump them here for now.
 126                          */
 127                         fsp_s: fsp-s {
 128                         };
 129                 };
 130
 131                 punit@0,1 {
 132                         u-boot,dm-pre-reloc;
 133                         reg = <0x00000800 0 0 0 0>;
 134                         compatible = "intel,apl-punit";
 135                 };
 136
 137                 p2sb: p2sb@d,0 {
 138                         u-boot,dm-pre-reloc;
 139                         reg = <0x02006810 0 0 0 0>;
 140                         compatible = "intel,p2sb";
 141                         early-regs = <IOMAP_P2SB_BAR 0x100000>;
 142
 143                         n {
 144                                 compatible = "intel,apl-pinctrl";
 145                                 u-boot,dm-pre-reloc;
 146                                 intel,p2sb-port-id = <PID_GPIO_N>;
 147                                 gpio_n: gpio-n {
 148                                         compatible = "intel,gpio";
 149                                         u-boot,dm-pre-reloc;
 150                                         gpio-controller;
 151                                         #gpio-cells = <2>;
 152                                 };
 153                         };
 154
 155                         nw {
 156                                 u-boot,dm-pre-reloc;
 157                                 compatible = "intel,apl-pinctrl";
 158                                 intel,p2sb-port-id = <PID_GPIO_NW>;
 159                                 #gpio-cells = <2>;
 160                                 gpio_nw: gpio-nw {
 161                                         compatible = "intel,gpio";
 162                                         u-boot,dm-pre-reloc;
 163                                         gpio-controller;
 164                                         #gpio-cells = <2>;
 165                                 };
 166                         };
 167
 168                         w {
 169                                 u-boot,dm-pre-reloc;
 170                                 compatible = "intel,apl-pinctrl";
 171                                 intel,p2sb-port-id = <PID_GPIO_W>;
 172                                 #gpio-cells = <2>;
 173                                 gpio_w: gpio-w {
 174                                         compatible = "intel,gpio";
 175                                         u-boot,dm-pre-reloc;
 176                                         gpio-controller;
 177                                         #gpio-cells = <2>;
 178                                 };
 179                         };
 180
 181                         sw {
 182                                 u-boot,dm-pre-reloc;
 183                                 compatible = "intel,apl-pinctrl";
 184                                 intel,p2sb-port-id = <PID_GPIO_SW>;
 185                                 #gpio-cells = <2>;
 186                                 gpio_sw: gpio-sw {
 187                                         compatible = "intel,gpio";
 188                                         u-boot,dm-pre-reloc;
 189                                         gpio-controller;
 190                                         #gpio-cells = <2>;
 191                                 };
 192                         };
 193
 194                         itss {
 195                                 u-boot,dm-pre-reloc;
 196                                 compatible = "intel,itss";
 197                                 intel,p2sb-port-id = <PID_ITSS>;
 198                                 intel,pmc-routes = <
 199                                         PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
 200                                         PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
 201                                         PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
 202                                         PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
 203                                         PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
 204                                         PMC_GPE_N_31_0 GPIO_GPE_N_31_0
 205                                         PMC_GPE_N_63_32 GPIO_GPE_N_63_32
 206                                         PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
 207                         };
 208                 };
 209
 210                 pmc@d,1 {
 211                         u-boot,dm-pre-reloc;
 212                         reg = <0x6900 0 0 0 0>;
 213
 214                         /*
 215                          * Values for BAR0, BAR2 and ACPI_BASE for when PCI
 216                          * auto-configure is not available
 217                          */
 218                         early-regs = <0xfe042000 0x2000
 219                                 0xfe044000 0x2000
 220                                 IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
 221                         compatible = "intel,apl-pmc";
 222                         gpe0-dwx-mask = <0xf>;
 223                         gpe0-dwx-shift-base = <4>;
 224
 225                         /*
 226                          * GPE configuration
 227                          * Note that GPE events called out in ASL code rely on
 228                          * this route, i.e., if this route changes then the
 229                          * affected GPE * offset bits also need to be changed.
 230                          * This sets the PMC register GPE_CFG fields.
 231                          */
 232                         gpe0-dw = <PMC_GPE_N_31_0
 233                                 PMC_GPE_N_63_32
 234                                 PMC_GPE_SW_31_0>;
 235                         gpe0-sts = <0x20>;
 236                         gpe0-en = <0x30>;
 237                 };
 238
 239                 spi: fast-spi@d,2 {
 240                         u-boot,dm-pre-reloc;
 241                         reg = <0x02006a10 0 0 0 0>;
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         compatible = "intel,fast-spi";
 245                         early-regs = <IOMAP_SPI_BASE 0x1000>;
 246                         intel,hardware-seq = <1>;
 247
 248                         fwstore_spi: spi-flash@0 {
 249                                 #size-cells = <1>;
 250                                 #address-cells = <1>;
 251                                 u-boot,dm-pre-reloc;
 252                                 reg = <0>;
 253                                 compatible = "winbond,w25q128fw",
 254                                          "jedec,spi-nor";
 255                                 rw-mrc-cache {
 256                                         label = "rw-mrc-cache";
 257                                         reg = <0x008e0000 0x00010000>;
 258                                         u-boot,dm-pre-reloc;
 259                                 };
 260                                 rw-var-mrc-cache {
 261                                         label = "rw-mrc-cache";
 262                                         reg = <0x008f0000 0x0001000>;
 263                                         u-boot,dm-pre-reloc;
 264                                 };
 265                         };
 266                 };
 267
 268                 i2c_0: i2c2@16,0 {
 269                         compatible = "intel,apl-i2c";
 270                         reg = <0x0200b010 0 0 0 0>;
 271                         clocks = <&clk CLK_I2C>;
 272                         i2c-scl-rising-time-ns = <104>;
 273                         i2c-scl-falling-time-ns = <52>;
 274                 };
 275
 276                 i2c_1: i2c2@16,1 {
 277                         compatible = "intel,apl-i2c";
 278                         reg = <0x0200b110 0 0 0 0>;
 279                         clocks = <&clk CLK_I2C>;
 280                         status = "disabled";
 281                 };
 282
 283                 i2c_2: i2c2@16,2 {
 284                         compatible = "intel,apl-i2c";
 285                         reg = <0x0200b210 0 0 0 0>;
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         clock-frequency = <400000>;
 289                         clocks = <&clk CLK_I2C>;
 290                         i2c-scl-rising-time-ns = <57>;
 291                         i2c-scl-falling-time-ns = <28>;
 292                         tpm@50 {
 293                                 reg = <0x50>;
 294                                 compatible = "google,cr50";
 295                                 u-boot,i2c-offset-len = <0>;
 296                                 ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
 297                                 interrupts-extended = <&acpi_gpe 0x3c 0>;
 298                         };
 299                 };
 300
 301                 i2c_3: i2c2@16,3 {
 302                         compatible = "intel,apl-i2c";
 303                         reg = <0x0200b110 0 0 0 0>;
 304                         clocks = <&clk CLK_I2C>;
 305                         i2c-scl-rising-time-ns = <76>;
 306                         i2c-scl-falling-time-ns = <164>;
 307                 };
 308
 309                 i2c_4: i2c2@17,0 {
 310                         compatible = "intel,apl-i2c";
 311                         reg = <0x0200b110 0 0 0 0>;
 312                         clocks = <&clk CLK_I2C>;
 313                         i2c-sda-hold-time-ns = <350>;
 314                         i2c-scl-rising-time-ns = <114>;
 315                         i2c-scl-falling-time-ns = <164>;
 316                 };
 317
 318                 i2c_5: i2c2@17,1 {
 319                         compatible = "intel,apl-i2c";
 320                         reg = <0x0200b110 0 0 0 0>;
 321                         clocks = <&clk CLK_I2C>;
 322                         i2c-scl-rising-time-ns = <76>;
 323                         i2c-scl-falling-time-ns = <164>;
 324                 };
 325
 326                 i2c_6: i2c2@17,2 {
 327                         compatible = "intel,apl-i2c";
 328                         reg = <0x0200b110 0 0 0 0>;
 329                         clocks = <&clk CLK_I2C>;
 330                         status = "disabled";
 331                 };
 332
 333                 i2c_7: i2c2@17,3 {
 334                         compatible = "intel,apl-i2c";
 335                         reg = <0x0200b110 0 0 0 0>;
 336                         clocks = <&clk CLK_I2C>;
 337                         status = "disabled";
 338                 };
 339
 340                 serial: serial@18,2 {
 341                         reg = <0x0200c210 0 0 0 0>;
 342                         u-boot,dm-pre-reloc;
 343                         compatible = "intel,apl-ns16550";
 344                         early-regs = <0xde000000 0x20>;
 345                         reg-shift = <2>;
 346                         clock-frequency = <1843200>;
 347                         current-speed = <115200>;
 348                 };
 349
 350                 pch: pch@1f,0 {
 351                         reg = <0x0000f800 0 0 0 0>;
 352                         compatible = "intel,apl-pch";
 353                         u-boot,dm-pre-reloc;
 354                         #address-cells = <1>;
 355                         #size-cells = <1>;
 356
 357                         lpc {
 358                                 compatible = "intel,apl-lpc";
 359                                 #address-cells = <1>;
 360                                 #size-cells = <0>;
 361                                 u-boot,dm-pre-reloc;
 362                                 cros_ec: cros-ec {
 363                                         u-boot,dm-pre-reloc;
 364                                         compatible = "google,cros-ec-lpc";
 365                                         reg = <0x204 1 0x200 1 0x880 0x80>;
 366
 367                                         /*
 368                                          * Describes the flash memory within
 369                                          * the EC
 370                                          */
 371                                         #address-cells = <1>;
 372                                         #size-cells = <1>;
 373                                         flash@8000000 {
 374                                                 reg = <0x08000000 0x20000>;
 375                                                 erase-value = <0xff>;
 376                                         };
 377                                 };
 378                         };
 379                 };
 380         };
 381
 382 };
 383
 384 &host_bridge {
 385         /*
 386          * PL1 override 12000 mW: the energy calculation is wrong with the
 387          * current VR solution. Experiments show that SoC TDP max (6W) can be
 388          * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
 389          */
 390         tdp-pl-override-mw = <12000 15000>;
 391
 392         early-pads = <
 393                 /* These two are for the debug UART */
 394                 GPIO_46 /* UART2 RX */
 395                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 396                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 397
 398                 GPIO_47 /* UART2 TX */
 399                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 400                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 401
 402                 GPIO_75 /* I2S1_BCLK -- PCH_WP */
 403                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
 404                         (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
 405
 406                 /* I2C2 - TPM  */
 407                 GPIO_128 /* LPSS_I2C2_SDA */
 408                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 409                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 410                 GPIO_129 /* LPSS_I2C2_SCL */
 411                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 412                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 413                 GPIO_28 /* TPM IRQ */
 414                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 415                                 PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
 416                                 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
 417                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
 418
 419                 /*
 420                  * WLAN_PE_RST - default to deasserted just in case FSP
 421                  * misbehaves
 422                  */
 423                 GPIO_122  /* SIO_SPI_2_RXD */
 424                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 425                                 PAD_CFG0_RX_DISABLE | 0)
 426                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 427
 428                 /* LPC */
 429                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 430                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 431                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 432                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 433                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 434                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 435                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 436                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 437                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 438                 >;
 439
 440         fspm,package = <PACKAGE_BGA>;
 441         fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
 442         fspm,memory-down = <MEMORY_DOWN_YES>;
 443         fspm,scrambler-support = <1>;
 444         fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
 445         fspm,channel-hash-mask = <0x36>;
 446         fspm,slice-hash-mask = <0x9>;
 447         fspm,dual-rank-support-enable = <1>;
 448         fspm,low-memory-max-value = <2048>;
 449         fspm,ch0-rank-enable = <1>;
 450         fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
 451         fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 452         fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
 453                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 454         fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 455         fspm,ch1-rank-enable = <1>;
 456         fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
 457         fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 458         fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
 459                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 460         fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 461         fspm,ch2-rank-enable = <1>;
 462         fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
 463         fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 464         fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
 465                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 466         fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 467         fspm,ch3-rank-enable = <1>;
 468         fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
 469         fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 470         fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
 471                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 472         fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 473         fspm,fspm,skip-cse-rbp = <1>;
 474
 475         fspm,ch-bit-swizzling = /bits/ 8 <
 476                 /* LP4_PHYS_CH0A */
 477
 478                 /* DQA[0:7] pins of LPDDR4 module */
 479                 6 7 5 4 3 1 0 2
 480                 /* DQA[8:15] pins of LPDDR4 module */
 481                 12 10 11 13 14 8 9 15
 482                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 483                 16 22 23 20 18 17 19 21
 484                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 485                 30 28 29 25 24 26 27 31
 486
 487                 /* LP4_PHYS_CH0B */
 488                 /* DQA[0:7] pins of LPDDR4 module */
 489                 7 3 5 2 6 0 1 4
 490                 /* DQA[8:15] pins of LPDDR4 module */
 491                  9 14 12 13 10 11 8 15
 492                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 493                 20 22 23 16 19 17 18 21
 494                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 495                 28 24 26 27 29 30 31 25
 496
 497                 /* LP4_PHYS_CH1A */
 498
 499                 /* DQA[0:7] pins of LPDDR4 module */
 500                 2 1 6 7 5 4 3 0
 501                 /* DQA[8:15] pins of LPDDR4 module */
 502                 11 10 8 9 12 15 13 14
 503                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 504                 17 23 19 16 21 22 20 18
 505                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 506                 31 29 26 25 28 27 24 30
 507
 508                 /* LP4_PHYS_CH1B */
 509
 510                 /* DQA[0:7] pins of LPDDR4 module */
 511                 4 3 7 5 6 1 0 2
 512                 /* DQA[8:15] pins of LPDDR4 module */
 513                 15 9 8 11 14 13 12 10
 514                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 515                 20 23 22 21 18 19 16 17
 516                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 517                 25 28 30 31 26 27 24 29>;
 518 };
 519
 520 &fsp_s {
 521         u-boot,dm-pre-proper;
 522
 523         /* Disable unused clkreq of PCIe root ports */
 524         pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */
 525                 CLKREQ_DISABLED
 526                 CLKREQ_DISABLED
 527                 CLKREQ_DISABLED
 528                 CLKREQ_DISABLED
 529                 CLKREQ_DISABLED>;
 530
 531         /*
 532          * GPIO for PERST_0
 533          * If the Board has PERST_0 signal, assign the GPIO
 534          * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
 535          *
 536          * This are not used yet, so comment them out for now.
 537          *
 538          * prt0-gpio = <GPIO_122>;
 539          *
 540          * GPIO for SD card detect
 541          * sdcard-cd-gpio = <GPIO_177>;
 542          */
 543
 544         /*
 545          * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
 546          * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
 547          *
 548          * EMMC TX DATA Delay 1
 549          * Refer to EDS-Vol2-22.3
 550          * [14:8] steps of delay for HS400, each 125ps
 551          * [6:0] steps of delay for SDR104/HS200, each 125ps
 552
 553         /*
 554          * EMMC TX DATA Delay 2
 555          * Refer to EDS-Vol2-22.3.
 556          * [30:24] steps of delay for SDR50, each 125ps
 557          * [22:16] steps of delay for DDR50, each 125ps
 558          * [14:8] steps of delay for SDR25/HS50, each 125ps
 559          * [6:0] steps of delay for SDR12, each 125ps
 560          */
 561
 562         /*
 563          * EMMC RX CMD/DATA Delay 1
 564          * Refer to EDS-Vol2-22.3.
 565          * [30:24] steps of delay for SDR50, each 125ps
 566          * [22:16] steps of delay for DDR50, each 125ps
 567          * [14:8] steps of delay for SDR25/HS50, each 125ps
 568          * [6:0] steps of delay for SDR12, each 125ps
 569          */
 570
 571         /*
 572          * EMMC RX CMD/DATA Delay 2
 573          * Refer to EDS-Vol2-22.3.
 574          * [17:16] stands for Rx Clock before Output Buffer
 575          * [14:8] steps of delay for Auto Tuning Mode, each 125ps
 576          * [6:0] steps of delay for HS200, each 125ps
 577          */
 578         emmc = <0x0c16 0x28162828 0x00181717 0x10008>;
 579
 580         /* Enable DPTF */
 581         dptf-enable;
 582
 583         /* Enable Audio Clock and Power gating */
 584         hdaudio-clk-gate-enable;
 585         hdaudio-pwr-gate-enable;
 586         hdaudio-bios-config-lockdown;
 587
 588         /* Enable lpss s0ix */
 589         lpss-s0ix-enable;
 590
 591         /*
 592          * TODO(sjg@chromium.org): Move this to the I2C nodes
 593          * Intel Common SoC Config
 594          *+-------------------+---------------------------+
 595          *| Field             |  Value                    |
 596          *+-------------------+---------------------------+
 597          *| I2C0              | Audio                     |
 598          *| I2C2              | TPM                       |
 599          *| I2C3              | Touchscreen               |
 600          *| I2C4              | Trackpad                  |
 601          *| I2C5              | Digitizer                 |
 602          *+-------------------+---------------------------+
 603          *
 604         common_soc_config" = "{
 605                 .i2c[0] = {
 606                         .speed = I2C_SPEED_FAST,
 607                         .rise-time-ns = 104,
 608                         .fall-time-ns = 52,
 609                 },
 610                 .i2c[2] = {
 611                         .early_init = 1,
 612                         .speed = I2C_SPEED_FAST,
 613                         .rise-time-ns = 57,
 614                         .fall-time-ns = 28,
 615                 },
 616                 .i2c[3] = {
 617                         .speed = I2C_SPEED_FAST,
 618                         .rise-time-ns = 76,
 619                         .fall-time-ns = 164,
 620                 },
 621                 .i2c[4] = {
 622                         .speed = I2C_SPEED_FAST,
 623                         .rise-time-ns = 114,
 624                         .fall-time-ns = 164,
 625                         .data_hold_time_ns = 350,
 626                 },
 627                 .i2c[5] = {
 628                         .speed = I2C_SPEED_FAST,
 629                         .rise-time-ns = 152,
 630                         .fall-time-ns = 30,
 631                 },
 632         }"
 633         */
 634
 635         /* Minimum SLP S3 assertion width 28ms */
 636         slp-s3-assertion-width-usecs = <28000>;
 637
 638         pads = <
 639                 /* PCIE_WAKE[0:3]_N */
 640                 PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
 641                 PAD_CFG_GPI(GPIO_206, UP_20K, DEEP)      /* Unused */
 642                 PAD_CFG_GPI(GPIO_207, UP_20K, DEEP)      /* Unused */
 643                 PAD_CFG_GPI(GPIO_208, UP_20K, DEEP)      /* Unused */
 644
 645                 /* EMMC interface */
 646                 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
 647                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
 648                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
 649                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
 650                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
 651                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
 652                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
 653                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
 654                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
 655                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
 656                 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
 657
 658                 /* SDIO -- unused */
 659                 PAD_CFG_GPI(GPIO_166, UP_20K, DEEP)      /* SDIO_CLK */
 660                 PAD_CFG_GPI(GPIO_167, UP_20K, DEEP)      /* SDIO_D0 */
 661                 /* Configure SDIO to enable power gating */
 662                 PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
 663                 PAD_CFG_GPI(GPIO_169, UP_20K, DEEP)      /* SDIO_D2 */
 664                 PAD_CFG_GPI(GPIO_170, UP_20K, DEEP)      /* SDIO_D3 */
 665                 PAD_CFG_GPI(GPIO_171, UP_20K, DEEP)      /* SDIO_CMD */
 666
 667                 /* SDCARD */
 668                 /* Pull down clock by 20K */
 669                 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
 670                 PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
 671                 PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
 672                 PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
 673                 PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
 674                 /* Card detect is active LOW with external pull up */
 675                 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
 676                 PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
 677                 /* CLK feedback, internal signal, needs 20K pull down */
 678                 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
 679                 /* No h/w write proect for uSD cards, pull down by 20K */
 680                 PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
 681                 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
 682                 PAD_CFG_GPO(GPIO_183, 0, DEEP)           /* SDIO_PWR_DOWN_N */
 683
 684                 /* SMBus -- unused */
 685                 PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP)    /* SMB_ALERT _N */
 686                 PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP)       /* SMB_CLK */
 687                 PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP)      /* SMB_DATA */
 688
 689                 /* LPC */
 690                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 691                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 692                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 693                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 694                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 695                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 696                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 697                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 698                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 699
 700                 /* I2C0 - Audio */
 701                 PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
 702                 PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
 703
 704                 /* I2C1 - NFC with external pulls */
 705                 PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
 706                 PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
 707
 708                 /* I2C2 - TPM  */
 709                 PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
 710                 PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
 711
 712                 /* I2C3 - touch */
 713                 PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
 714                 PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
 715
 716                 /* I2C4 - trackpad */
 717                 /* LPSS_I2C4_SDA */
 718                 PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
 719                 /* LPSS_I2C4_SCL */
 720                 PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
 721
 722                 /* I2C5 -- pen with external pulls  */
 723                 PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
 724                 PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
 725
 726                 /* I2C6-7 -- unused */
 727                 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP)      /* LPSS_I2C6_SDA */
 728                 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP)      /* LPSS_I2C6_SCL */
 729                 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP)      /* LPSS_I2C7_SDA */
 730                 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP)      /* LPSS_I2C7_SCL */
 731
 732                 /* Audio Amp - I2S6 */
 733                 PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
 734                 PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
 735                 PAD_CFG_GPI(GPIO_148, UP_20K, DEEP)      /* ISH_GPIO_2 - unused */
 736                 PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
 737
 738                 /* NFC Reset */
 739                 PAD_CFG_GPO(GPIO_150, 1, DEEP)           /* ISH_GPIO_4 */
 740
 741                 PAD_CFG_GPI(GPIO_151, UP_20K, DEEP)      /* ISH_GPIO_5 - unused */
 742
 743                 /* Touch enable */
 744                 PAD_CFG_GPO(GPIO_152, 1, DEEP)           /* ISH_GPIO_6 */
 745
 746                 PAD_CFG_GPI(GPIO_153, UP_20K, DEEP)      /* ISH_GPIO_7 - unused */
 747                 PAD_CFG_GPI(GPIO_154, UP_20K, DEEP)      /* ISH_GPIO_8 - unused */
 748                 PAD_CFG_GPI(GPIO_155, UP_20K, DEEP)      /* ISH_GPIO_9 - unused */
 749
 750                 /* PCIE_CLKREQ[0:3]_N */
 751                 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1)    /* WLAN with external pull */
 752                 PAD_CFG_GPI(GPIO_210, UP_20K, DEEP)      /* unused */
 753                 PAD_CFG_GPI(GPIO_211, UP_20K, DEEP)      /* unused */
 754                 PAD_CFG_GPI(GPIO_212, UP_20K, DEEP)      /* unused */
 755
 756                 /* OSC_CLK_OUT_[0:4] -- unused */
 757                 PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
 758                 PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
 759                 PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
 760                 PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
 761                 PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
 762
 763                 /* PMU Signals */
 764                 PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
 765                 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
 766                 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
 767                 PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
 768                 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
 769                 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
 770                 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
 771                 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
 772                 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
 773                 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP)         /* EN_PP3300_EMMC */
 774                 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
 775                 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
 776
 777                 /* DDI[0:1] SDA and SCL -- unused */
 778                 PAD_CFG_GPI(GPIO_187, UP_20K, DEEP)      /* HV_DDI0_DDC_SDA */
 779                 PAD_CFG_GPI(GPIO_188, UP_20K, DEEP)      /* HV_DDI0_DDC_SCL */
 780                 PAD_CFG_GPI(GPIO_189, UP_20K, DEEP)      /* HV_DDI1_DDC_SDA */
 781                 PAD_CFG_GPI(GPIO_190, UP_20K, DEEP)      /* HV_DDI1_DDC_SCL */
 782
 783                 /* MIPI I2C -- unused */
 784                 PAD_CFG_GPI(GPIO_191, UP_20K, DEEP)      /* MIPI_I2C_SDA */
 785                 PAD_CFG_GPI(GPIO_192, UP_20K, DEEP)      /* MIPI_I2C_SCL */
 786
 787                 /* Panel 0 control */
 788                 PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
 789                 PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
 790                 PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
 791
 792                 /* Panel 1 control -- unused */
 793                 PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
 794                 PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
 795                 PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
 796
 797                 /* Hot plug detect */
 798                 PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
 799                 PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
 800
 801                 /* MDSI signals -- unused */
 802                 PAD_CFG_GPI(GPIO_201, UP_20K, DEEP)      /* MDSI_A_TE */
 803                 PAD_CFG_GPI(GPIO_202, UP_20K, DEEP)      /* MDSI_A_TE */
 804
 805                 /* USB overcurrent pins */
 806                 PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
 807                 PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
 808
 809                 /* PMC SPI -- almost entirely unused */
 810                 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
 811                 PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
 812                 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
 813                 PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
 814                 PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
 815                 PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
 816
 817                 /* PMIC Signals Unused signals related to an old PMIC interface */
 818                 PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
 819                 PAD_CFG_GPI(GPIO_213, NONE, DEEP)        /* unused external pull */
 820                 PAD_CFG_GPI(GPIO_214, UP_20K, DEEP)      /* unused */
 821                 PAD_CFG_GPI(GPIO_215, UP_20K, DEEP)      /* unused */
 822                 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
 823                 PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP)    /* unused */
 824                 PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
 825                 PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
 826                 PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
 827
 828                 /* I2S1 -- largely unused */
 829                 PAD_CFG_GPI(GPIO_74, UP_20K, DEEP)      /* I2S1_MCLK */
 830                 PAD_CFG_GPI(GPIO_75, UP_20K, DEEP)      /* I2S1_BCLK -- PCH_WP */
 831                 PAD_CFG_GPO(GPIO_76, 0, DEEP)           /* I2S1_WS_SYNC -- SPK_PA_EN */
 832                 PAD_CFG_GPI(GPIO_77, UP_20K, DEEP)      /* I2S1_SDI */
 833                 PAD_CFG_GPO(GPIO_78, 1, DEEP)           /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
 834
 835                 /* DMIC or I2S4 */
 836                 /* AVS_DMIC_CLK_A1 */
 837                 PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
 838                 PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
 839                 PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1)  /* AVS_DMIC_DATA_1 */
 840                 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP)       /* unused -- strap */
 841                 PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
 842
 843                 /* I2S2 -- Headset amp */
 844                 PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1)   /* AVS_I2S2_MCLK */
 845                 PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1)   /* AVS_I2S2_BCLK */
 846                 PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1)   /* AVS_I2S2_SW_SYNC */
 847                 PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDI */
 848                 PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDO */
 849
 850                 /* I2S3 -- largely unused */
 851                 PAD_CFG_GPI(GPIO_89, UP_20K, DEEP)       /* unused */
 852                 PAD_CFG_GPI(GPIO_90, UP_20K, DEEP)       /* GPS_HOST_WAKE */
 853                 PAD_CFG_GPO(GPIO_91, 1, DEEP)            /* GPS_EN */
 854                 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP)       /* unused -- strap */
 855
 856                 /* Fast SPI */
 857                 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
 858                 PAD_CFG_GPI(GPIO_98, UP_20K, DEEP)                              /* FST_SPI_CS1_B -- unused */
 859                 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
 860                 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_MISO_IO1 */
 861                 PAD_CFG_GPI(GPIO_101, NONE, DEEP)                               /* FST_IO2 -- MEM_CONFIG0 */
 862                 PAD_CFG_GPI(GPIO_102, NONE, DEEP)                               /* FST_IO3 -- MEM_CONFIG1 */
 863                 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_CLK */
 864                 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
 865                 PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE)        /* FST_SPI_CS2_N */
 866
 867                 /* SIO_SPI_0 - Used for FP */
 868                 PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_CLK */
 869                 PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_FS0 */
 870                 PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_RXD */
 871                 PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_TXD */
 872
 873                 /* SIO_SPI_1 -- largely unused */
 874                 PAD_CFG_GPI(GPIO_111, UP_20K, DEEP)      /* SIO_SPI_1_CLK */
 875                 PAD_CFG_GPI(GPIO_112, UP_20K, DEEP)      /* SIO_SPI_1_FS0 */
 876                 PAD_CFG_GPI(GPIO_113, UP_20K, DEEP)      /* SIO_SPI_1_FS1 */
 877                 /* Headset interrupt */
 878                 PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
 879                 PAD_CFG_GPI(GPIO_117, UP_20K, DEEP)      /* SIO_SPI_1_TXD */
 880
 881                 /* SIO_SPI_2 -- unused */
 882                 PAD_CFG_GPI(GPIO_118, UP_20K, DEEP)      /* SIO_SPI_2_CLK */
 883                 PAD_CFG_GPI(GPIO_119, UP_20K, DEEP)      /* SIO_SPI_2_FS0 */
 884                 PAD_CFG_GPI(GPIO_120, UP_20K, DEEP)      /* SIO_SPI_2_FS1 */
 885                 PAD_CFG_GPI(GPIO_121, UP_20K, DEEP)      /* SIO_SPI_2_FS2 */
 886                 /* WLAN_PE_RST - default to deasserted */
 887                 PAD_CFG_GPO(GPIO_122, 0, DEEP)           /* SIO_SPI_2_RXD */
 888                 PAD_CFG_GPI(GPIO_123, UP_20K, DEEP)      /* SIO_SPI_2_TXD */
 889
 890                 /* Debug tracing */
 891                 PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
 892                 PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
 893                 PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
 894                 PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL)        /* FP_INT */
 895                 PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
 896                 PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
 897                 PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
 898                 PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
 899                 PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
 900
 901                 PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
 902                 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP)       /* Board phase enforcement */
 903                 PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI  */
 904                 PAD_CFG_GPI(GPIO_12, UP_20K, DEEP)       /* unused */
 905                 PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
 906                 PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
 907                 PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE)    /* TRACKPAD_INT_1V8_ODL */
 908                 PAD_CFG_GPI(GPIO_16, UP_20K, DEEP)       /* unused */
 909                 PAD_CFG_GPI(GPIO_17, UP_20K, DEEP)       /* 1 vs 4 DMIC config */
 910                 PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
 911                 PAD_CFG_GPI(GPIO_19, UP_20K, DEEP)       /* unused */
 912                 PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
 913                 PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
 914                 PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
 915                 PAD_CFG_GPI(GPIO_23, UP_20K, DEEP)       /* unused */
 916                 PAD_CFG_GPI(GPIO_24, NONE, DEEP)         /* PEN_PDCT_ODL */
 917                 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP)       /* unused */
 918                 PAD_CFG_GPI(GPIO_26, UP_20K, DEEP)       /* unused */
 919                 PAD_CFG_GPI(GPIO_27, UP_20K, DEEP)       /* unused */
 920                 PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
 921                 PAD_CFG_GPO(GPIO_29, 1, DEEP)            /* FP reset */
 922                 PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
 923                 PAD_CFG_GPO(GPIO_31, 0, DEEP)            /* NFC FW DL */
 924                 PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5)     /* SUS_CLK2 */
 925                 PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
 926                 PAD_CFG_GPI(GPIO_34, UP_20K, DEEP)       /* unused */
 927                 PAD_CFG_GPO(GPIO_35, 0, DEEP)            /* PEN_RESET - active high */
 928                 PAD_CFG_GPO(GPIO_36, 0, DEEP)            /* touch reset */
 929                 PAD_CFG_GPI(GPIO_37, UP_20K, DEEP)       /* unused */
 930
 931                 /* LPSS_UART[0:2] */
 932                 PAD_CFG_GPI(GPIO_38, NONE, DEEP)         /* LPSS_UART0_RXD - MEM_CONFIG2*/
 933                 /* Next 2 are straps */
 934                 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP)       /* LPSS_UART0_TXD - unused */
 935                 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP)       /* LPSS_UART0_RTS - unused */
 936                 PAD_CFG_GPI(GPIO_41, NONE, DEEP)         /* LPSS_UART0_CTS - EC_IN_RW */
 937                 PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1)   /* LPSS_UART1_RXD */
 938                 PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1)   /* LPSS_UART1_TXD */
 939                 PAD_CFG_GPO(GPIO_44, 1, DEEP)    /* GPS_RST_ODL */
 940                 PAD_CFG_GPI(GPIO_45, NONE, DEEP)         /* LPSS_UART1_CTS - MEM_CONFIG3 */
 941                 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1)   /* LPSS_UART2_RXD */
 942                 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
 943                 PAD_CFG_GPI(GPIO_48, UP_20K, DEEP)       /* LPSS_UART2_RTS - unused */
 944                 PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
 945
 946                 /* Camera interface -- completely unused */
 947                 PAD_CFG_GPI(GPIO_62, UP_20K, DEEP)       /* GP_CAMERASB00 */
 948                 PAD_CFG_GPI(GPIO_63, UP_20K, DEEP)       /* GP_CAMERASB01 */
 949                 PAD_CFG_GPI(GPIO_64, UP_20K, DEEP)       /* GP_CAMERASB02 */
 950                 PAD_CFG_GPI(GPIO_65, UP_20K, DEEP)       /* GP_CAMERASB03 */
 951                 PAD_CFG_GPI(GPIO_66, UP_20K, DEEP)       /* GP_CAMERASB04 */
 952                 PAD_CFG_GPI(GPIO_67, UP_20K, DEEP)       /* GP_CAMERASB05 */
 953                 PAD_CFG_GPI(GPIO_68, UP_20K, DEEP)       /* GP_CAMERASB06 */
 954                 PAD_CFG_GPI(GPIO_69, UP_20K, DEEP)       /* GP_CAMERASB07 */
 955                 PAD_CFG_GPI(GPIO_70, UP_20K, DEEP)       /* GP_CAMERASB08 */
 956                 PAD_CFG_GPI(GPIO_71, UP_20K, DEEP)       /* GP_CAMERASB09 */
 957                 PAD_CFG_GPI(GPIO_72, UP_20K, DEEP)       /* GP_CAMERASB10 */
 958                 PAD_CFG_GPI(GPIO_73, UP_20K, DEEP)       /* GP_CAMERASB11 */
 959         >;
 960 };