1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
12 #include <asm/cache.h>
13 #include <asm/mrccache.h>
16 #include <asm/arch/mrc.h>
17 #include <asm/arch/msg_port.h>
18 #include <asm/arch/quark.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
24 struct mrc_data_container *cache;
25 struct mrc_region entry;
28 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
32 cache = mrccache_find_current(&entry);
36 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
37 cache->data, cache->data_size, cache->checksum);
39 /* copy mrc cache to the mrc_params */
40 memcpy(&mrc_params->timings, cache->data, cache->data_size);
45 static int mrc_configure_params(struct mrc_params *mrc_params)
47 const void *blob = gd->fdt_blob;
51 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
53 debug("%s: Cannot find MRC node\n", __func__);
57 #ifdef CONFIG_ENABLE_MRC_CACHE
58 mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
59 if (mrc_params->boot_mode)
60 mrc_params->boot_mode = BM_COLD;
62 mrc_params->boot_mode = BM_FAST;
64 mrc_params->boot_mode = BM_COLD;
70 * We need determine ECC by pin strap state
72 * Disable ECC by default for now
74 mrc_params->ecc_enables = 0;
76 mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
77 if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
78 mrc_params->scrambling_enables = 1;
80 mrc_params->scrambling_enables = 0;
82 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
83 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
84 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);
86 mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
87 mrc_params->channel_enables = fdtdec_get_int(blob, node,
89 mrc_params->channel_width = fdtdec_get_int(blob, node,
91 mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);
93 mrc_params->refresh_rate = fdtdec_get_int(blob, node,
95 mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
97 mrc_params->ron_value = fdtdec_get_int(blob, node,
99 mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
101 mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
104 mrc_params->params.density = fdtdec_get_int(blob, node,
106 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
107 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
108 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
109 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
110 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);
112 debug("MRC dram_width %d\n", mrc_params->dram_width);
113 debug("MRC rank_enables %d\n", mrc_params->rank_enables);
114 debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
115 debug("MRC flags: %s\n",
116 (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");
118 debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
119 mrc_params->params.density, mrc_params->params.cl,
120 mrc_params->params.ras, mrc_params->params.wtr,
121 mrc_params->params.rrd, mrc_params->params.faw);
128 struct mrc_params mrc_params;
129 #ifdef CONFIG_ENABLE_MRC_CACHE
134 memset(&mrc_params, 0, sizeof(struct mrc_params));
135 ret = mrc_configure_params(&mrc_params);
139 /* Set up the DRAM by calling the memory reference code */
140 mrc_init(&mrc_params);
141 if (mrc_params.status)
144 gd->ram_size = mrc_params.mem_size;
145 post_code(POST_DRAM);
147 /* variable range MTRR#2: RAM area */
149 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
150 0 | MTRR_TYPE_WRBACK);
151 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
152 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
155 #ifdef CONFIG_ENABLE_MRC_CACHE
156 cache = malloc(sizeof(struct mrc_timings));
158 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
160 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
162 mrc->len = sizeof(struct mrc_timings);
169 int dram_init_banksize(void)
171 gd->bd->bi_dram[0].start = 0;
172 gd->bd->bi_dram[0].size = gd->ram_size;
178 * This function looks for the highest region of memory lower than 4GB which
179 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
180 * It overrides the default implementation found elsewhere which simply
181 * picks the end of ram, wherever that may be. The location of the stack,
182 * the relocation address, and how far U-Boot is moved by relocation are
183 * set in the global data structure.
185 ulong board_get_usable_ram_top(ulong total_size)