1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
5 * Based on code from the coreboot file of the same name
15 #include <asm/atomic.h>
17 #include <asm/interrupt.h>
18 #include <asm/lapic.h>
19 #include <asm/microcode.h>
23 #include <asm/processor.h>
25 #include <dm/device-internal.h>
26 #include <dm/uclass-internal.h>
29 #include <linux/delay.h>
30 #include <linux/linkage.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 /* Total CPUs include BSP */
37 /* This also needs to match the sipi.S assembly code for saved MSR encoding */
45 struct mp_flight_plan {
47 struct mp_flight_record *records;
50 static struct mp_flight_plan mp_info;
58 static inline void barrier_wait(atomic_t *b)
60 while (atomic_read(b) == 0)
65 static inline void release_barrier(atomic_t *b)
71 static inline void stop_this_cpu(void)
73 /* Called by an AP when it is ready to halt and wait for a new task */
78 /* Returns 1 if timeout waiting for APs. 0 if target APs found */
79 static int wait_for_aps(atomic_t *val, int target, int total_delay,
85 while (atomic_read(val) != target) {
87 delayed += delay_step;
88 if (delayed >= total_delay) {
97 static void ap_do_flight_plan(struct udevice *cpu)
101 for (i = 0; i < mp_info.num_records; i++) {
102 struct mp_flight_record *rec = &mp_info.records[i];
104 atomic_inc(&rec->cpus_entered);
105 barrier_wait(&rec->barrier);
107 if (rec->ap_call != NULL)
108 rec->ap_call(cpu, rec->ap_arg);
112 static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
117 for (uclass_find_first_device(UCLASS_CPU, &dev);
119 uclass_find_next_device(&dev)) {
120 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
122 if (plat->cpu_id == apic_id) {
132 * By the time APs call ap_init() caching has been setup, and microcode has
135 static void ap_init(unsigned int cpu_index)
141 /* Ensure the local apic is enabled */
145 ret = find_cpu_by_apic_id(apic_id, &dev);
147 debug("Unknown CPU apic_id %x\n", apic_id);
151 debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
152 dev ? dev->name : "(apic_id not found)");
154 /* Walk the flight plan */
155 ap_do_flight_plan(dev);
163 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
164 MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
165 MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
166 MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
167 MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
170 static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
174 msr = msr_read(index);
175 entry->index = index;
179 /* Return the next entry */
184 static int save_bsp_msrs(char *start, int size)
188 struct saved_msr *msr_entry;
192 /* Determine number of MTRRs need to be saved */
193 msr = msr_read(MTRR_CAP_MSR);
194 num_var_mtrrs = msr.lo & 0xff;
196 /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
197 msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
199 if ((msr_count * sizeof(struct saved_msr)) > size) {
200 printf("Cannot mirror all %d msrs\n", msr_count);
204 msr_entry = (void *)start;
205 for (i = 0; i < NUM_FIXED_MTRRS; i++)
206 msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
208 for (i = 0; i < num_var_mtrrs; i++) {
209 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
210 msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
213 msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
218 static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
220 struct sipi_params_16bit *params16;
221 struct sipi_params *params;
222 static char msr_save[512];
229 /* Copy in the code */
230 code_len = ap_start16_code_end - ap_start16;
231 debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
233 memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
235 addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
236 params16 = (struct sipi_params_16bit *)addr;
237 params16->ap_start = (uint32_t)ap_start;
238 params16->gdt = (uint32_t)gd->arch.gdt;
239 params16->gdt_limit = X86_GDT_SIZE - 1;
240 debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
242 params = (struct sipi_params *)sipi_params;
243 debug("SIPI 32-bit params at %p\n", params);
244 params->idt_ptr = (uint32_t)x86_get_idt();
246 params->stack_size = CONFIG_AP_STACK_SIZE;
247 size = params->stack_size * num_cpus;
248 stack = memalign(4096, size);
251 params->stack_top = (u32)(stack + size);
252 #if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
253 !defined(CONFIG_INTEL_MID)
254 params->microcode_ptr = ucode_base;
255 debug("Microcode at %x\n", params->microcode_ptr);
257 params->msr_table_ptr = (u32)msr_save;
258 ret = save_bsp_msrs(msr_save, sizeof(msr_save));
261 params->msr_count = ret;
263 params->c_handler = (uint32_t)&ap_init;
265 *ap_countp = ¶ms->ap_count;
266 atomic_set(*ap_countp, 0);
267 debug("SIPI vector is ready\n");
272 static int check_cpu_devices(int expected_cpus)
276 for (i = 0; i < expected_cpus; i++) {
280 ret = uclass_find_device(UCLASS_CPU, i, &dev);
282 debug("Cannot find CPU %d in device tree\n", i);
290 /* Returns 1 for timeout. 0 on success */
291 static int apic_wait_timeout(int total_delay, const char *msg)
295 if (!(lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY))
298 debug("Waiting for %s...", msg);
299 while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
302 if (total >= total_delay) {
303 debug("timed out: aborting\n");
312 static int start_aps(int ap_count, atomic_t *num_aps)
315 /* Max location is 4KiB below 1MiB */
316 const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
321 /* The vector is sent as a 4k aligned address in one byte */
322 sipi_vector = AP_DEFAULT_BASE >> 12;
324 if (sipi_vector > max_vector_loc) {
325 printf("SIPI vector too large! 0x%08x\n",
330 debug("Attempting to start %d APs\n", ap_count);
332 if (apic_wait_timeout(1000, "ICR not to be busy"))
335 /* Send INIT IPI to all but self */
336 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
337 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
339 debug("Waiting for 10ms after sending INIT\n");
343 if (apic_wait_timeout(1000, "ICR not to be busy"))
346 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
347 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
348 LAPIC_DM_STARTUP | sipi_vector);
349 if (apic_wait_timeout(10000, "first SIPI to complete"))
352 /* Wait for CPUs to check in up to 200 us */
353 wait_for_aps(num_aps, ap_count, 200, 15);
356 if (apic_wait_timeout(1000, "ICR not to be busy"))
359 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
360 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
361 LAPIC_DM_STARTUP | sipi_vector);
362 if (apic_wait_timeout(10000, "second SIPI to complete"))
365 /* Wait for CPUs to check in */
366 if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
367 debug("Not all APs checked in: %d/%d\n",
368 atomic_read(num_aps), ap_count);
375 static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
379 const int timeout_us = 100000;
380 const int step_us = 100;
381 int num_aps = num_cpus - 1;
383 for (i = 0; i < mp_params->num_records; i++) {
384 struct mp_flight_record *rec = &mp_params->flight_plan[i];
386 /* Wait for APs if the record is not released */
387 if (atomic_read(&rec->barrier) == 0) {
388 /* Wait for the APs to check in */
389 if (wait_for_aps(&rec->cpus_entered, num_aps,
390 timeout_us, step_us)) {
391 debug("MP record %d timeout\n", i);
396 if (rec->bsp_call != NULL)
397 rec->bsp_call(cpu, rec->bsp_arg);
399 release_barrier(&rec->barrier);
404 static int init_bsp(struct udevice **devp)
406 char processor_name[CPU_MAX_NAME_LEN];
410 cpu_get_name(processor_name);
411 debug("CPU: %s\n", processor_name);
414 ret = find_cpu_by_apic_id(apic_id, devp);
416 printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
423 int mp_init(struct mp_params *p)
430 /* This will cause the CPUs devices to be bound */
432 ret = uclass_get(UCLASS_CPU, &uc);
436 if (IS_ENABLED(CONFIG_QFW)) {
437 ret = qemu_cpu_fixup();
442 ret = init_bsp(&cpu);
444 debug("Cannot init boot CPU: err=%d\n", ret);
448 if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
449 printf("Invalid MP parameters\n");
453 num_cpus = cpu_get_count(cpu);
455 debug("Cannot get number of CPUs: err=%d\n", num_cpus);
460 debug("Warning: Only 1 CPU is detected\n");
462 ret = check_cpu_devices(num_cpus);
464 debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
466 /* Copy needed parameters so that APs have a reference to the plan */
467 mp_info.num_records = p->num_records;
468 mp_info.records = p->flight_plan;
470 /* Load the SIPI vector */
471 ret = load_sipi_vector(&ap_count, num_cpus);
472 if (ap_count == NULL)
476 * Make sure SIPI data hits RAM so the APs that come up will see
477 * the startup code even if the caches are disabled
481 /* Start the APs providing number of APs and the cpus_entered field */
482 num_aps = num_cpus - 1;
483 ret = start_aps(num_aps, ap_count);
486 debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
491 /* Walk the flight plan for the BSP */
492 ret = bsp_do_flight_plan(cpu, p);
494 debug("CPU init failed: err=%d\n", ret);
501 int mp_init_cpu(struct udevice *cpu, void *unused)
503 struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
506 * Multiple APs are brought up simultaneously and they may get the same
507 * seq num in the uclass_resolve_seq() during device_probe(). To avoid
508 * this, set req_seq to the reg number in the device tree in advance.
510 cpu->req_seq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(cpu), "reg",
512 plat->ucode_version = microcode_read_rev();
513 plat->device_id = gd->arch.x86_device;
515 return device_probe(cpu);