arch/x86/cpu/ivybridge/sata.c

   1 /*
   2  * From Coreboot
   3  * Copyright (C) 2008-2009 coresystems GmbH
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <asm/io.h>
  12 #include <asm/pci.h>
  13 #include <asm/arch/pch.h>
  14 #include <asm/arch/bd82x6x.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static inline u32 sir_read(pci_dev_t dev, int idx)
  19 {
  20         x86_pci_write_config32(dev, SATA_SIRI, idx);
  21         return x86_pci_read_config32(dev, SATA_SIRD);
  22 }
  23
  24 static inline void sir_write(pci_dev_t dev, int idx, u32 value)
  25 {
  26         x86_pci_write_config32(dev, SATA_SIRI, idx);
  27         x86_pci_write_config32(dev, SATA_SIRD, value);
  28 }
  29
  30 static void common_sata_init(pci_dev_t dev, unsigned int port_map)
  31 {
  32         u32 reg32;
  33         u16 reg16;
  34
  35         /* Set IDE I/O Configuration */
  36         reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  37         x86_pci_write_config32(dev, IDE_CONFIG, reg32);
  38
  39         /* Port enable */
  40         reg16 = x86_pci_read_config16(dev, 0x92);
  41         reg16 &= ~0x3f;
  42         reg16 |= port_map;
  43         x86_pci_write_config16(dev, 0x92, reg16);
  44
  45         /* SATA Initialization register */
  46         port_map &= 0xff;
  47         x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
  48 }
  49
  50 static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
  51 {
  52         unsigned int port_map, speed_support, port_tx;
  53         struct pci_controller *hose = pci_bus_to_hose(0);
  54         const char *mode;
  55         u32 reg32;
  56         u16 reg16;
  57
  58         debug("SATA: Initializing...\n");
  59
  60         /* SATA configuration */
  61         port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
  62         speed_support = fdtdec_get_int(blob, node,
  63                                        "sata_interface_speed_support", 0);
  64
  65         /* Enable BARs */
  66         x86_pci_write_config16(dev, PCI_COMMAND, 0x0007);
  67
  68         mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
  69         if (!mode || !strcmp(mode, "ahci")) {
  70                 u32 abar;
  71
  72                 debug("SATA: Controller in AHCI mode\n");
  73
  74                 /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
  75                 x86_pci_write_config8(dev, INTR_LN, 0x0a);
  76
  77                 /* Set timings */
  78                 x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
  79                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
  80                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
  81                 x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
  82                                 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
  83
  84                 /* Sync DMA */
  85                 x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
  86                 x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
  87
  88                 common_sata_init(dev, 0x8000 | port_map);
  89
  90                 /* Initialize AHCI memory-mapped space */
  91                 abar = pci_read_bar32(hose, dev, 5);
  92                 debug("ABAR: %08X\n", abar);
  93                 /* CAP (HBA Capabilities) : enable power management */
  94                 reg32 = readl(abar + 0x00);
  95                 reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
  96                 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
  97                 /* Set ISS, if available */
  98                 if (speed_support) {
  99                         reg32 &= ~0x00f00000;
 100                         reg32 |= (speed_support & 0x03) << 20;
 101                 }
 102                 writel(reg32, abar + 0x00);
 103                 /* PI (Ports implemented) */
 104                 writel(port_map, abar + 0x0c);
 105                 (void) readl(abar + 0x0c); /* Read back 1 */
 106                 (void) readl(abar + 0x0c); /* Read back 2 */
 107                 /* CAP2 (HBA Capabilities Extended)*/
 108                 reg32 = readl(abar + 0x24);
 109                 reg32 &= ~0x00000002;
 110                 writel(reg32, abar + 0x24);
 111                 /* VSP (Vendor Specific Register */
 112                 reg32 = readl(abar + 0xa0);
 113                 reg32 &= ~0x00000005;
 114                 writel(reg32, abar + 0xa0);
 115         } else if (!strcmp(mode, "combined")) {
 116                 debug("SATA: Controller in combined mode\n");
 117
 118                 /* No AHCI: clear AHCI base */
 119                 pci_write_bar32(hose, dev, 5, 0x00000000);
 120                 /* And without AHCI BAR no memory decoding */
 121                 reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
 122                 reg16 &= ~PCI_COMMAND_MEMORY;
 123                 x86_pci_write_config16(dev, PCI_COMMAND, reg16);
 124
 125                 x86_pci_write_config8(dev, 0x09, 0x80);
 126
 127                 /* Set timings */
 128                 x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 129                                 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
 130                 x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 131                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 132                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
 133
 134                 /* Sync DMA */
 135                 x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
 136                 x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
 137
 138                 common_sata_init(dev, port_map);
 139         } else {
 140                 debug("SATA: Controller in plain-ide mode\n");
 141
 142                 /* No AHCI: clear AHCI base */
 143                 pci_write_bar32(hose, dev, 5, 0x00000000);
 144
 145                 /* And without AHCI BAR no memory decoding */
 146                 reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
 147                 reg16 &= ~PCI_COMMAND_MEMORY;
 148                 x86_pci_write_config16(dev, PCI_COMMAND, reg16);
 149
 150                 /*
 151                  * Native mode capable on both primary and secondary (0xa)
 152                  * OR'ed with enabled (0x50) = 0xf
 153                  */
 154                 x86_pci_write_config8(dev, 0x09, 0x8f);
 155
 156                 /* Set Interrupt Line */
 157                 /* Interrupt Pin is set by D31IP.PIP */
 158                 x86_pci_write_config8(dev, INTR_LN, 0xff);
 159
 160                 /* Set timings */
 161                 x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 162                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 163                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
 164                 x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 165                                 IDE_SITRE | IDE_ISP_3_CLOCKS |
 166                                 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
 167
 168                 /* Sync DMA */
 169                 x86_pci_write_config16(dev, IDE_SDMA_CNT,
 170                                        IDE_SSDE0 | IDE_PSDE0);
 171                 x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
 172
 173                 common_sata_init(dev, port_map);
 174         }
 175
 176         /* Set Gen3 Transmitter settings if needed */
 177         port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
 178         if (port_tx)
 179                 pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
 180
 181         port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
 182         if (port_tx)
 183                 pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
 184
 185         /* Additional Programming Requirements */
 186         sir_write(dev, 0x04, 0x00001600);
 187         sir_write(dev, 0x28, 0xa0000033);
 188         reg32 = sir_read(dev, 0x54);
 189         reg32 &= 0xff000000;
 190         reg32 |= 0x5555aa;
 191         sir_write(dev, 0x54, reg32);
 192         sir_write(dev, 0x64, 0xcccc8484);
 193         reg32 = sir_read(dev, 0x68);
 194         reg32 &= 0xffff0000;
 195         reg32 |= 0xcccc;
 196         sir_write(dev, 0x68, reg32);
 197         reg32 = sir_read(dev, 0x78);
 198         reg32 &= 0x0000ffff;
 199         reg32 |= 0x88880000;
 200         sir_write(dev, 0x78, reg32);
 201         sir_write(dev, 0x84, 0x001c7000);
 202         sir_write(dev, 0x88, 0x88338822);
 203         sir_write(dev, 0xa0, 0x001c7000);
 204         sir_write(dev, 0xc4, 0x0c0c0c0c);
 205         sir_write(dev, 0xc8, 0x0c0c0c0c);
 206         sir_write(dev, 0xd4, 0x10000000);
 207
 208         pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
 209         pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
 210 }
 211
 212 static void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
 213 {
 214         unsigned port_map;
 215         const char *mode;
 216         u16 map = 0;
 217
 218         /*
 219          * Set SATA controller mode early so the resource allocator can
 220          * properly assign IO/Memory resources for the controller.
 221          */
 222         mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
 223         if (mode && !strcmp(mode, "ahci"))
 224                 map = 0x0060;
 225         port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
 226
 227         map |= (port_map ^ 0x3f) << 8;
 228         x86_pci_write_config16(dev, 0x90, map);
 229 }
 230
 231 static int bd82x6x_sata_probe(struct udevice *dev)
 232 {
 233         if (!(gd->flags & GD_FLG_RELOC))
 234                 bd82x6x_sata_enable(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset);
 235         else
 236                 bd82x6x_sata_init(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset);
 237
 238         return 0;
 239 }
 240
 241 static const struct udevice_id bd82x6x_ahci_ids[] = {
 242         { .compatible = "intel,pantherpoint-ahci" },
 243         { }
 244 };
 245
 246 U_BOOT_DRIVER(ahci_ivybridge_drv) = {
 247         .name           = "ahci_ivybridge",
 248         .id             = UCLASS_DISK,
 249         .of_match       = bd82x6x_ahci_ids,
 250         .probe          = bd82x6x_sata_probe,
 251 };