2 * From coreboot southbridge/intel/bd82x6x/lpc.c
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * SPDX-License-Identifier: GPL-2.0
16 #include <asm/interrupt.h>
18 #include <asm/ioapic.h>
20 #include <asm/arch/pch.h>
24 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
25 #define TEST_SMM_FLASH_LOCKDOWN 0
27 static int pch_enable_apic(struct udevice *pch)
32 /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
33 dm_pci_write_config8(pch, ACPI_CNTL, 0x80);
35 writel(0, IO_APIC_INDEX);
36 writel(1 << 25, IO_APIC_DATA);
38 /* affirm full set of redirection table entries ("write once") */
39 writel(1, IO_APIC_INDEX);
40 reg32 = readl(IO_APIC_DATA);
41 writel(1, IO_APIC_INDEX);
42 writel(reg32, IO_APIC_DATA);
44 writel(0, IO_APIC_INDEX);
45 reg32 = readl(IO_APIC_DATA);
46 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
47 if (reg32 != (1 << 25)) {
48 printf("APIC Error - cannot write to registers\n");
52 debug("Dumping IOAPIC registers\n");
53 for (i = 0; i < 3; i++) {
54 writel(i, IO_APIC_INDEX);
55 debug(" reg 0x%04x:", i);
56 reg32 = readl(IO_APIC_DATA);
57 debug(" 0x%08x\n", reg32);
60 /* Select Boot Configuration register. */
61 writel(3, IO_APIC_INDEX);
63 /* Use Processor System Bus to deliver interrupts. */
64 writel(1, IO_APIC_DATA);
69 static void pch_enable_serial_irqs(struct udevice *pch)
73 /* Set packet length and toggle silent mode bit for one frame. */
74 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
75 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
76 dm_pci_write_config8(pch, SERIRQ_CNTL, value);
78 dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6));
82 static int pch_pirq_init(struct udevice *pch)
84 uint8_t route[8], *ptr;
86 if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
87 "intel,pirq-routing", route, sizeof(route)))
90 dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++);
91 dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++);
92 dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++);
93 dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);
95 dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++);
96 dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++);
97 dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++);
98 dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);
101 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
102 * here. It's unclear if it is needed
107 static int pch_gpi_routing(struct udevice *pch)
113 if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
114 "intel,gpi-routing", route, sizeof(route)))
117 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
118 reg |= route[gpi] << (gpi * 2);
120 dm_pci_write_config32(pch, 0xb8, reg);
125 static int pch_power_options(struct udevice *pch)
127 const void *blob = gd->fdt_blob;
128 int node = pch->of_offset;
138 * Which state do we want to goto after g3 (power restored)?
142 * If the option is not existent (Laptops), use Kconfig setting.
143 * TODO(sjg@chromium.org): Make this configurable
145 pwr_on = MAINBOARD_POWER_ON;
147 dm_pci_read_config16(pch, GEN_PMCON_3, ®16);
150 case MAINBOARD_POWER_OFF:
154 case MAINBOARD_POWER_ON:
158 case MAINBOARD_POWER_KEEP:
160 state = "state keep";
166 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
167 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
170 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
172 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
174 dm_pci_write_config16(pch, GEN_PMCON_3, reg16);
175 debug("Set power %s after power failure.\n", state);
177 /* Set up NMI on errors. */
179 reg8 &= 0x0f; /* Higher Nibble must be 0 */
180 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
181 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
185 /* TODO(sjg@chromium.org): Make this configurable */
186 nmi_option = NMI_OFF;
188 debug("NMI sources enabled.\n");
189 reg8 &= ~(1 << 7); /* Set NMI. */
191 debug("NMI sources disabled.\n");
192 /* Can't mask NMI from PCI-E and NMI_NOW */
197 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
198 dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
199 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
200 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
201 #if DEBUG_PERIODIC_SMIS
202 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
203 reg16 |= (3 << 0); /* Periodic SMI every 8s */
205 dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
207 /* Set the board's GPI routing. */
208 ret = pch_gpi_routing(pch);
212 dm_pci_read_config16(pch, 0x40, &pmbase);
215 writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
216 "intel,gpe0-enable", 0));
217 writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
218 "intel,alt-gp-smi-enable", 0));
220 /* Set up power management block and determine sleep mode */
221 reg32 = inl(pmbase + 0x04); /* PM1_CNT */
222 reg32 &= ~(7 << 10); /* SLP_TYP */
223 reg32 |= (1 << 0); /* SCI_EN */
224 outl(reg32, pmbase + 0x04);
226 /* Clear magic status bits to prevent unexpected wake */
227 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
228 clrbits_le32(RCB_REG(0x3f02), 0xf);
233 static void pch_rtc_init(struct udevice *pch)
238 dm_pci_read_config8(pch, GEN_PMCON_3, ®8);
239 rtc_failed = reg8 & RTC_BATTERY_DEAD;
241 reg8 &= ~RTC_BATTERY_DEAD;
242 dm_pci_write_config8(pch, GEN_PMCON_3, reg8);
244 debug("rtc_failed = 0x%x\n", rtc_failed);
246 /* TODO: Handle power failure */
248 printf("RTC power failed\n");
251 /* CougarPoint PCH Power Management init */
252 static void cpt_pm_init(struct udevice *pch)
254 debug("CougarPoint PM init\n");
255 dm_pci_write_config8(pch, 0xa9, 0x47);
256 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
258 setbits_le32(RCB_REG(0x228c), 1 << 0);
259 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
260 setbits_le32(RCB_REG(0x0900), 1 << 14);
261 writel(0xc0388400, RCB_REG(0x2304));
262 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
263 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
264 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
265 writel(0x050f0000, RCB_REG(0x3318));
266 writel(0x04000000, RCB_REG(0x3324));
267 setbits_le32(RCB_REG(0x3340), 0xfffff);
268 setbits_le32(RCB_REG(0x3344), 1 << 1);
270 writel(0x0001c000, RCB_REG(0x3360));
271 writel(0x00061100, RCB_REG(0x3368));
272 writel(0x7f8fdfff, RCB_REG(0x3378));
273 writel(0x000003fc, RCB_REG(0x337c));
274 writel(0x00001000, RCB_REG(0x3388));
275 writel(0x0001c000, RCB_REG(0x3390));
276 writel(0x00000800, RCB_REG(0x33a0));
277 writel(0x00001000, RCB_REG(0x33b0));
278 writel(0x00093900, RCB_REG(0x33c0));
279 writel(0x24653002, RCB_REG(0x33cc));
280 writel(0x062108fe, RCB_REG(0x33d0));
281 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
282 writel(0x01010000, RCB_REG(0x3a28));
283 writel(0x01010404, RCB_REG(0x3a2c));
284 writel(0x01041041, RCB_REG(0x3a80));
285 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
286 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
287 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
288 writel(0x00000001, RCB_REG(0x3a6c));
289 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
290 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
291 writel(0, RCB_REG(0x33c8));
292 setbits_le32(RCB_REG(0x21b0), 0xf);
295 /* PantherPoint PCH Power Management init */
296 static void ppt_pm_init(struct udevice *pch)
298 debug("PantherPoint PM init\n");
299 dm_pci_write_config8(pch, 0xa9, 0x47);
300 setbits_le32(RCB_REG(0x2238), 1 << 0);
301 setbits_le32(RCB_REG(0x228c), 1 << 0);
302 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
303 setbits_le16(RCB_REG(0x0900), 1 << 14);
304 writel(0xc03b8400, RCB_REG(0x2304));
305 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
306 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
307 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
308 writel(0x054f0000, RCB_REG(0x3318));
309 writel(0x04000000, RCB_REG(0x3324));
310 setbits_le32(RCB_REG(0x3340), 0xfffff);
311 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
312 writel(0x0001c000, RCB_REG(0x3360));
313 writel(0x00061100, RCB_REG(0x3368));
314 writel(0x7f8fdfff, RCB_REG(0x3378));
315 writel(0x000003fd, RCB_REG(0x337c));
316 writel(0x00001000, RCB_REG(0x3388));
317 writel(0x0001c000, RCB_REG(0x3390));
318 writel(0x00000800, RCB_REG(0x33a0));
319 writel(0x00001000, RCB_REG(0x33b0));
320 writel(0x00093900, RCB_REG(0x33c0));
321 writel(0x24653002, RCB_REG(0x33cc));
322 writel(0x067388fe, RCB_REG(0x33d0));
323 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
324 writel(0x01010000, RCB_REG(0x3a28));
325 writel(0x01010404, RCB_REG(0x3a2c));
326 writel(0x01040000, RCB_REG(0x3a80));
327 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
328 /* SATA 2/3 disabled */
329 setbits_le32(RCB_REG(0x3a84), 1 << 24);
330 /* SATA 4/5 disabled */
331 setbits_le32(RCB_REG(0x3a88), 1 << 0);
332 writel(0x00000001, RCB_REG(0x3a6c));
333 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
334 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
335 setbits_le32(RCB_REG(0x33a4), (1 << 0));
336 writel(0, RCB_REG(0x33c8));
337 setbits_le32(RCB_REG(0x21b0), 0xf);
340 static void enable_hpet(void)
342 /* Move HPET to default address 0xfed00000 and enable it */
343 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
346 static void enable_clock_gating(struct udevice *pch)
351 setbits_le32(RCB_REG(0x2234), 0xf);
353 dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
354 reg16 |= (1 << 2) | (1 << 11);
355 dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
357 pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
358 pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
359 pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
360 pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
362 reg32 = readl(RCB_REG(CG));
364 reg32 |= (1 << 29) | (1 << 28);
365 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
375 writel(reg32, RCB_REG(CG));
377 setbits_le32(RCB_REG(0x38c0), 0x7);
378 setbits_le32(RCB_REG(0x36d4), 0x6680c004);
379 setbits_le32(RCB_REG(0x3564), 0x3);
382 #if CONFIG_HAVE_SMI_HANDLER
383 static void pch_lock_smm(pci_dev_t dev)
385 #if TEST_SMM_FLASH_LOCKDOWN
389 if (acpi_slp_type != 3) {
390 #if ENABLE_ACPI_MODE_IN_COREBOOT
391 debug("Enabling ACPI via APMC:\n");
392 outb(0xe1, 0xb2); /* Enable ACPI mode */
395 debug("Disabling ACPI via APMC:\n");
396 outb(0x1e, 0xb2); /* Disable ACPI mode */
401 /* Don't allow evil boot loaders, kernels, or
402 * userspace applications to deceive us:
406 #if TEST_SMM_FLASH_LOCKDOWN
408 debug("Locking BIOS to RO... ");
409 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
410 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
411 (reg8 & 1) ? "rw" : "ro");
412 reg8 &= ~(1 << 0); /* clear BIOSWE */
413 x86_pci_write_config8(dev, 0xdc, reg8);
414 reg8 |= (1 << 1); /* set BLE */
415 x86_pci_write_config8(dev, 0xdc, reg8);
417 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
418 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
419 (reg8 & 1) ? "rw" : "ro");
422 writeb(0, 0xfff00000);
424 reg8 |= (1 << 0); /* set BIOSWE */
425 x86_pci_write_config8(dev, 0xdc, reg8);
427 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
428 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
429 (reg8 & 1) ? "rw" : "ro");
435 static void pch_disable_smm_only_flashing(struct udevice *pch)
439 debug("Enabling BIOS updates outside of SMM... ");
440 dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */
442 dm_pci_write_config8(pch, 0xdc, reg8);
445 static void pch_fixups(struct udevice *pch)
449 /* Indicate DRAM init done for MRC S3 to know it can resume */
450 dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2);
451 gen_pmcon_2 |= (1 << 7);
452 dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);
454 /* Enable DMI ASPM in the PCH */
455 clrbits_le32(RCB_REG(0x2304), 1 << 10);
456 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
457 setbits_le32(RCB_REG(0x21a8), 0x3);
461 * Enable Prefetching and Caching.
463 static void enable_spi_prefetch(struct udevice *pch)
467 dm_pci_read_config8(pch, 0xdc, ®8);
469 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
470 dm_pci_write_config8(pch, 0xdc, reg8);
473 static void enable_port80_on_lpc(struct udevice *pch)
475 /* Enable port 80 POST on LPC */
476 dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
477 clrbits_le32(RCB_REG(GCS), 4);
480 static void set_spi_speed(void)
484 /* Observe SPI Descriptor Component Section 0 */
485 writel(0x1000, RCB_REG(SPI_DESC_COMP0));
487 /* Extract the1 Write/Erase SPI Frequency from descriptor */
488 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
492 /* Set Software Sequence frequency to match */
493 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
497 * lpc_early_init() - set up LPC serial ports and other early things
500 * @return 0 if OK, -ve on error
502 static int lpc_early_init(struct udevice *dev)
511 count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
512 "intel,gen-dec", (u32 *)values,
513 sizeof(values) / sizeof(u32));
517 /* Set COM1/COM2 decode range */
518 dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
520 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
521 dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
522 GAMEL_LPC_EN | COMA_LPC_EN);
524 /* Write all registers but use 0 if we run out of data */
525 count = count * sizeof(u32) / sizeof(values[0]);
526 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
530 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
531 dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
534 enable_spi_prefetch(dev->parent);
536 /* This is already done in start.S, but let's do it in C */
537 enable_port80_on_lpc(dev->parent);
544 static int lpc_init_extra(struct udevice *dev)
546 struct udevice *pch = dev->parent;
547 const void *blob = gd->fdt_blob;
550 debug("pch: lpc_init\n");
551 dm_pci_write_bar32(pch, 0, 0);
552 dm_pci_write_bar32(pch, 1, 0xff800000);
553 dm_pci_write_bar32(pch, 2, 0xfec00000);
554 dm_pci_write_bar32(pch, 3, 0x800);
555 dm_pci_write_bar32(pch, 4, 0x900);
557 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
561 /* Set the value for PCI command register. */
562 dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
564 /* IO APIC initialization. */
565 pch_enable_apic(pch);
567 pch_enable_serial_irqs(pch);
569 /* Setup the PIRQ. */
572 /* Setup power options. */
573 pch_power_options(pch);
575 /* Initialize power management */
576 switch (pch_silicon_type(pch)) {
577 case PCH_TYPE_CPT: /* CougarPoint */
580 case PCH_TYPE_PPT: /* PantherPoint */
584 printf("Unknown Chipset: %s\n", pch->name);
588 /* Initialize the real time clock. */
591 /* Initialize the High Precision Event Timers, if present. */
594 /* Initialize Clock Gating */
595 enable_clock_gating(pch);
597 pch_disable_smm_only_flashing(pch);
599 #if CONFIG_HAVE_SMI_HANDLER
608 static int bd82x6x_lpc_early_init(struct udevice *dev)
610 /* Setting up Southbridge. In the northbridge code. */
611 debug("Setting up static southbridge registers\n");
612 dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
613 dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
615 /* Enable ACPI BAR */
616 dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80);
618 debug("Disabling watchdog reboot\n");
619 setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
620 outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
622 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
623 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
628 static int bd82x6x_lpc_probe(struct udevice *dev)
632 if (!(gd->flags & GD_FLG_RELOC)) {
633 ret = lpc_early_init(dev);
635 debug("%s: lpc_early_init() failed\n", __func__);
639 return bd82x6x_lpc_early_init(dev);
642 return lpc_init_extra(dev);
645 static const struct udevice_id bd82x6x_lpc_ids[] = {
646 { .compatible = "intel,bd82x6x-lpc" },
650 U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
653 .of_match = bd82x6x_lpc_ids,
654 .probe = bd82x6x_lpc_probe,