2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/lapic.h>
14 #include <asm/arch/bd82x6x.h>
15 #include <asm/arch/model_206ax.h>
16 #include <asm/arch/pch.h>
17 #include <asm/arch/sandybridge.h>
19 #define BIOS_CTRL 0xdc
21 static int bd82x6x_probe(struct udevice *dev)
23 const void *blob = gd->fdt_blob;
24 struct pci_controller *hose;
28 if (!(gd->flags & GD_FLG_RELOC))
31 hose = pci_bus_to_hose(0);
32 lpc_enable(PCH_LPC_DEV);
33 lpc_init_extra(hose, PCH_LPC_DEV);
35 /* Cause the SATA device to do its init */
36 uclass_first_device(UCLASS_DISK, &dev);
38 bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
39 bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
41 gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
43 debug("%s: Cannot find GMA node\n", __func__);
46 ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
49 ret = gma_func0_init(dev, blob, gma_node);
56 static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
60 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
61 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
62 rcba = rcba & 0xffffc000;
63 *sbasep = rcba + 0x3800;
68 static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
73 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
77 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
78 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
80 bios_cntl &= ~BIOS_CTRL_BIOSWE;
83 bios_cntl |= BIOS_CTRL_BIOSWE;
86 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
91 static const struct pch_ops bd82x6x_pch_ops = {
92 .get_sbase = bd82x6x_pch_get_sbase,
93 .get_version = bd82x6x_pch_get_version,
94 .set_spi_protect = bd82x6x_set_spi_protect,
97 static const struct udevice_id bd82x6x_ids[] = {
98 { .compatible = "intel,bd82x6x" },
102 U_BOOT_DRIVER(bd82x6x_drv) = {
105 .of_match = bd82x6x_ids,
106 .probe = bd82x6x_probe,
107 .ops = &bd82x6x_pch_ops,