arch/x86/cpu/intel_common/p2sb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Primary-to-Sideband Bridge
   4  *
   5  * Copyright 2019 Google LLC
   6  */
   7
   8 #define LOG_CATEGORY UCLASS_P2SB
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <dt-structs.h>
  13 #include <log.h>
  14 #include <p2sb.h>
  15 #include <spl.h>
  16 #include <asm/pci.h>
  17 #include <linux/bitops.h>
  18
  19 struct p2sb_platdata {
  20 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  21         struct dtd_intel_p2sb dtplat;
  22 #endif
  23         ulong mmio_base;
  24         pci_dev_t bdf;
  25 };
  26
  27 /* PCI config space registers */
  28 #define HPTC_OFFSET             0x60
  29 #define HPTC_ADDR_ENABLE_BIT    BIT(7)
  30
  31 /* High Performance Event Timer Configuration */
  32 #define P2SB_HPTC                               0x60
  33 #define P2SB_HPTC_ADDRESS_ENABLE                BIT(7)
  34
  35 /*
  36  * ADDRESS_SELECT            ENCODING_RANGE
  37  *      0                 0xfed0 0000 - 0xfed0 03ff
  38  *      1                 0xfed0 1000 - 0xfed0 13ff
  39  *      2                 0xfed0 2000 - 0xfed0 23ff
  40  *      3                 0xfed0 3000 - 0xfed0 33ff
  41  */
  42 #define P2SB_HPTC_ADDRESS_SELECT_0              (0 << 0)
  43 #define P2SB_HPTC_ADDRESS_SELECT_1              (1 << 0)
  44 #define P2SB_HPTC_ADDRESS_SELECT_2              (2 << 0)
  45 #define P2SB_HPTC_ADDRESS_SELECT_3              (3 << 0)
  46
  47 /*
  48  * p2sb_early_init() - Enable decoding for HPET range
  49  *
  50  * This is needed by FSP-M which uses the High Precision Event Timer.
  51  *
  52  * @dev: P2SB device
  53  * @return 0 if OK, -ve on error
  54  */
  55 static int p2sb_early_init(struct udevice *dev)
  56 {
  57         struct p2sb_platdata *plat = dev_get_platdata(dev);
  58         pci_dev_t pdev = plat->bdf;
  59
  60         /*
  61          * Enable decoding for HPET memory address range.
  62          * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
  63          * the High Performance Timer memory address range
  64          * selected by bits 1:0
  65          */
  66         pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
  67                              PCI_SIZE_8);
  68
  69         /* Enable PCR Base address in PCH */
  70         pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
  71                              PCI_SIZE_32);
  72         pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
  73
  74         /* Enable P2SB MSE */
  75         pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
  76                              PCI_COMMAND_MEMORY, PCI_SIZE_8);
  77
  78         return 0;
  79 }
  80
  81 static int p2sb_spl_init(struct udevice *dev)
  82 {
  83         /* Enable decoding for HPET. Needed for FSP global pointer storage */
  84         dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
  85                             P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
  86
  87         return 0;
  88 }
  89
  90 int p2sb_ofdata_to_platdata(struct udevice *dev)
  91 {
  92         struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
  93         struct p2sb_platdata *plat = dev_get_platdata(dev);
  94
  95 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  96         int ret;
  97         u32 base[2];
  98
  99         ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
 100         if (ret)
 101                 return log_msg_ret("Missing/short early-regs", ret);
 102         plat->mmio_base = base[0];
 103         /* TPL sets up the initial BAR */
 104         if (spl_phase() == PHASE_TPL) {
 105                 plat->bdf = pci_get_devfn(dev);
 106                 if (plat->bdf < 0)
 107                         return log_msg_ret("Cannot get p2sb PCI address",
 108                                            plat->bdf);
 109         }
 110         upriv->mmio_base = plat->mmio_base;
 111 #else
 112         plat->mmio_base = plat->dtplat.early_regs[0];
 113         plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
 114         upriv->mmio_base = plat->mmio_base;
 115 #endif
 116
 117         return 0;
 118 }
 119
 120 static int p2sb_probe(struct udevice *dev)
 121 {
 122         if (spl_phase() == PHASE_TPL)
 123                 return p2sb_early_init(dev);
 124         else if (spl_phase() == PHASE_SPL)
 125                 return p2sb_spl_init(dev);
 126
 127         return 0;
 128 }
 129
 130 static int p2sb_child_post_bind(struct udevice *dev)
 131 {
 132 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 133         struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
 134         int ret;
 135         u32 pid;
 136
 137         ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
 138         if (ret)
 139                 return ret;
 140         pplat->pid = pid;
 141 #endif
 142
 143         return 0;
 144 }
 145
 146 static const struct udevice_id p2sb_ids[] = {
 147         { .compatible = "intel,p2sb" },
 148         { }
 149 };
 150
 151 U_BOOT_DRIVER(p2sb_drv) = {
 152         .name           = "intel_p2sb",
 153         .id             = UCLASS_P2SB,
 154         .of_match       = p2sb_ids,
 155         .probe          = p2sb_probe,
 156         .ofdata_to_platdata = p2sb_ofdata_to_platdata,
 157         .platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
 158         .per_child_platdata_auto_alloc_size =
 159                 sizeof(struct p2sb_child_platdata),
 160         .child_post_bind = p2sb_child_post_bind,
 161 };