1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
9 #include <asm/cpu_common.h>
10 #include <asm/intel_regs.h>
11 #include <asm/lapic.h>
12 #include <asm/lpc_common.h>
16 #include <asm/microcode.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 static int report_bist_failure(void)
22 if (gd->arch.bist != 0) {
23 post_code(POST_BIST_FAILURE);
24 printf("BIST failed: %08x\n", gd->arch.bist);
31 int cpu_common_init(void)
33 struct udevice *dev, *lpc;
36 /* Halt if there was a built in self test failure */
37 ret = report_bist_failure();
43 ret = microcode_update_intel();
44 if (ret && ret != -EEXIST) {
45 debug("%s: Microcode update failure (err=%d)\n", __func__, ret);
49 /* Enable upper 128bytes of CMOS */
50 writel(1 << 2, RCB_REG(RC));
52 /* Early chipset init required before RAM init can work */
53 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
55 ret = uclass_first_device(UCLASS_LPC, &lpc);
61 /* Cause the SATA device to do its early init */
62 uclass_first_device(UCLASS_AHCI, &dev);
67 int cpu_set_flex_ratio_to_tdp_nominal(void)
69 msr_t flex_ratio, msr;
72 /* Check for Flex Ratio support */
73 flex_ratio = msr_read(MSR_FLEX_RATIO);
74 if (!(flex_ratio.lo & FLEX_RATIO_EN))
77 /* Check for >0 configurable TDPs */
78 msr = msr_read(MSR_PLATFORM_INFO);
79 if (((msr.hi >> 1) & 3) == 0)
82 /* Use nominal TDP ratio for flex ratio */
83 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
84 nominal_ratio = msr.lo & 0xff;
86 /* See if flex ratio is already set to nominal TDP ratio */
87 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
90 /* Set flex ratio to nominal TDP ratio */
91 flex_ratio.lo &= ~0xff00;
92 flex_ratio.lo |= nominal_ratio << 8;
93 flex_ratio.lo |= FLEX_RATIO_LOCK;
94 msr_write(MSR_FLEX_RATIO, flex_ratio);
96 /* Set flex ratio in soft reset data register bits 11:6 */
97 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
98 (nominal_ratio & 0x3f) << 6);
100 debug("CPU: Soft reset to set up flex ratio\n");
102 /* Set soft reset control to use register value */
103 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
105 /* Issue warm reset, will be "CPU only" due to soft reset data */
106 outb(0x0, IO_PORT_RESET);
107 outb(SYS_RST | RST_CPU, IO_PORT_RESET);