x86: apl: Add SPL loaders
[oweals/u-boot.git] / arch / x86 / cpu / apollolake / spl.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2019 Google LLC
4  */
5
6 #include <common.h>
7 #include <binman_sym.h>
8 #include <dm.h>
9 #include <spi.h>
10 #include <spl.h>
11 #include <spi_flash.h>
12 #include <asm/fast_spi.h>
13 #include <asm/spl.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/iomap.h>
16 #include <dm/device-internal.h>
17 #include <dm/uclass-internal.h>
18
19 /* This reads the next phase from mapped SPI flash */
20 static int rom_load_image(struct spl_image_info *spl_image,
21                           struct spl_boot_device *bootdev)
22 {
23         ulong spl_pos = spl_get_image_pos();
24         ulong spl_size = spl_get_image_size();
25         struct udevice *dev;
26         ulong map_base;
27         size_t map_size;
28         uint offset;
29         int ret;
30
31         spl_image->size = CONFIG_SYS_MONITOR_LEN;  /* We don't know SPL size */
32         spl_image->entry_point = spl_phase() == PHASE_TPL ?
33                 CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
34         spl_image->load_addr = spl_image->entry_point;
35         spl_image->os = IH_OS_U_BOOT;
36         spl_image->name = "U-Boot";
37         debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
38
39         if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
40                 ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
41                 if (ret)
42                         return log_msg_ret("spi_flash", ret);
43                 if (!dev)
44                         return log_msg_ret("spi_flash dev", -ENODEV);
45                 ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
46                 if (ret)
47                         return log_msg_ret("mmap", ret);
48         } else {
49                 ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
50                                              &offset);
51                 if (ret)
52                         return ret;
53         }
54         spl_pos += map_base & ~0xff000000;
55         debug(", base %lx, pos %lx\n", map_base, spl_pos);
56         bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
57         memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
58         cpu_flush_l1d_to_l2();
59         bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
60
61         return 0;
62 }
63 SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
64
65 #if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
66
67 static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
68                               void *buf)
69 {
70         struct spi_flash *flash = dev_get_uclass_priv(dev);
71         struct mtd_info *mtd = &flash->mtd;
72         size_t retlen;
73
74         return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
75 }
76
77 static int apl_flash_probe(struct udevice *dev)
78 {
79         return spi_flash_std_probe(dev);
80 }
81
82 /*
83  * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
84  * need to allocate the parent_platdata since by the time this function is
85  * called device_bind() has already gone past that step.
86  */
87 static int apl_flash_bind(struct udevice *dev)
88 {
89         if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
90                 struct dm_spi_slave_platdata *plat;
91                 struct udevice *spi;
92                 int ret;
93
94                 ret = uclass_first_device_err(UCLASS_SPI, &spi);
95                 if (ret)
96                         return ret;
97                 dev->parent = spi;
98
99                 plat = calloc(sizeof(*plat), 1);
100                 if (!plat)
101                         return -ENOMEM;
102                 dev->parent_platdata = plat;
103         }
104
105         return 0;
106 }
107
108 static const struct dm_spi_flash_ops apl_flash_ops = {
109         .read           = apl_flash_std_read,
110 };
111
112 static const struct udevice_id apl_flash_ids[] = {
113         { .compatible = "jedec,spi-nor" },
114         { }
115 };
116
117 U_BOOT_DRIVER(winbond_w25q128fw) = {
118         .name           = "winbond_w25q128fw",
119         .id             = UCLASS_SPI_FLASH,
120         .of_match       = apl_flash_ids,
121         .bind           = apl_flash_bind,
122         .probe          = apl_flash_probe,
123         .priv_auto_alloc_size = sizeof(struct spi_flash),
124         .ops            = &apl_flash_ops,
125 };
126
127 /* This uses a SPI flash device to read the next phase */
128 static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
129                                    struct spl_boot_device *bootdev)
130 {
131         ulong spl_pos = spl_get_image_pos();
132         ulong spl_size = spl_get_image_size();
133         struct udevice *dev;
134         int ret;
135
136         ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
137         if (ret)
138                 return ret;
139
140         spl_image->size = CONFIG_SYS_MONITOR_LEN;  /* We don't know SPL size */
141         spl_image->entry_point = spl_phase() == PHASE_TPL ?
142                 CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
143         spl_image->load_addr = spl_image->entry_point;
144         spl_image->os = IH_OS_U_BOOT;
145         spl_image->name = "U-Boot";
146         spl_pos &= ~0xff000000;
147         debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
148         ret = spi_flash_read_dm(dev, spl_pos, spl_size,
149                                 (void *)spl_image->load_addr);
150         cpu_flush_l1d_to_l2();
151         if (ret)
152                 return ret;
153
154         return 0;
155 }
156 SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
157                       spl_fast_spi_load_image);
158
159 void board_boot_order(u32 *spl_boot_list)
160 {
161         bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
162
163         if (use_spi_flash) {
164                 spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
165                 spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
166         } else {
167                 spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
168                 spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
169         }
170 }
171
172 #else
173
174 void board_boot_order(u32 *spl_boot_list)
175 {
176         spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
177 }
178 #endif