1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
11 #include <asm/cpu_common.h>
12 #include <asm/intel_regs.h>
15 #include <asm/arch/systemagent.h>
16 #include <linux/delay.h>
19 * Punit Initialisation code. This all isn't documented, but
22 static int punit_init(struct udevice *dev)
29 /* Thermal throttle activation offset */
30 ret = uclass_first_device_err(UCLASS_CPU, &cpu);
32 return log_msg_ret("Cannot find CPU", ret);
33 cpu_configure_thermal_target(cpu);
36 * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
37 * Enable all cores here.
39 writel(0, MCHBAR_REG(CORE_DISABLE_MASK));
42 reg = readl(MCHBAR_REG(BIOS_RESET_CPL));
43 if (reg == 0xffffffff) {
44 /* P-unit not found */
45 debug("Punit MMIO not available\n");
49 /* Set Punit interrupt pin IPIN offset 3D */
50 dm_pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x2);
52 /* Set PUINT IRQ to 24 and INTPIN LOCK */
53 writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
54 PUINT_THERMAL_DEVICE_IRQ_LOCK,
55 MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ));
57 /* Stage0 BIOS Reset Complete (RST_CPL) */
58 enable_bios_reset_cpl();
61 * Poll for bit 8 to check if PCODE has completed its action in response
62 * to BIOS Reset complete. We wait here till 1 ms for the bit to get
66 while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) {
67 if (get_timer(start) > 1) {
68 debug("PCODE Init Done timeout\n");
73 debug("PUNIT init complete\n");
78 static int apl_punit_probe(struct udevice *dev)
80 if (spl_phase() == PHASE_SPL)
81 return punit_init(dev);
86 static const struct udevice_id apl_syscon_ids[] = {
87 { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT },
91 U_BOOT_DRIVER(syscon_intel_punit) = {
92 .name = "intel_punit_syscon",
94 .of_match = apl_syscon_ids,
95 .probe = apl_punit_probe,