1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
11 #include <asm/cpu_common.h>
12 #include <asm/intel_regs.h>
15 #include <asm/arch/systemagent.h>
18 * Punit Initialisation code. This all isn't documented, but
21 static int punit_init(struct udevice *dev)
28 /* Thermal throttle activation offset */
29 ret = uclass_first_device_err(UCLASS_CPU, &cpu);
31 return log_msg_ret("Cannot find CPU", ret);
32 cpu_configure_thermal_target(cpu);
35 * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
36 * Enable all cores here.
38 writel(0, MCHBAR_REG(CORE_DISABLE_MASK));
41 reg = readl(MCHBAR_REG(BIOS_RESET_CPL));
42 if (reg == 0xffffffff) {
43 /* P-unit not found */
44 debug("Punit MMIO not available\n");
48 /* Set Punit interrupt pin IPIN offset 3D */
49 dm_pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x2);
51 /* Set PUINT IRQ to 24 and INTPIN LOCK */
52 writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
53 PUINT_THERMAL_DEVICE_IRQ_LOCK,
54 MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ));
56 /* Stage0 BIOS Reset Complete (RST_CPL) */
57 enable_bios_reset_cpl();
60 * Poll for bit 8 to check if PCODE has completed its action in response
61 * to BIOS Reset complete. We wait here till 1 ms for the bit to get
65 while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) {
66 if (get_timer(start) > 1) {
67 debug("PCODE Init Done timeout\n");
72 debug("PUNIT init complete\n");
77 static int apl_punit_probe(struct udevice *dev)
79 if (spl_phase() == PHASE_SPL)
80 return punit_init(dev);
85 static const struct udevice_id apl_syscon_ids[] = {
86 { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT },
90 U_BOOT_DRIVER(syscon_intel_punit) = {
91 .name = "intel_punit_syscon",
93 .of_match = apl_syscon_ids,
94 .probe = apl_punit_probe,