1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
5 * From coreboot Apollo Lake support lpc.c
12 #include <asm/lpc_common.h>
14 #include <asm/arch/iomap.h>
15 #include <asm/arch/lpc.h>
16 #include <linux/log2.h>
18 void lpc_enable_fixed_io_ranges(uint io_enables)
20 pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables,
25 * Find the first unused IO window.
26 * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
28 static int find_unused_pmio_window(void)
33 for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
34 pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
37 if (!(lgir & LPC_LGIR_EN))
44 int lpc_open_pmio_window(uint base, uint size)
47 u32 lgir_reg_offset, lgir, window_size, alignment;
48 ulong bridged_size, bridge_base;
51 log_debug("LPC: Trying to open IO window from %x size %x\n", base,
57 while (bridged_size < size) {
58 /* Each IO range register can only open a 256-byte window */
59 window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE);
61 /* Window size must be a power of two for the AMASK to work */
62 alignment = 1UL << (order_base_2(window_size));
63 window_size = ALIGN(window_size, alignment);
65 /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */
66 lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
67 lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
69 /* Skip programming if same range already programmed */
70 for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
71 pci_x86_read_config(PCH_DEV_LPC,
72 LPC_GENERIC_IO_RANGE(i), ®,
78 lgir_reg_num = find_unused_pmio_window();
79 if (lgir_reg_num < 0) {
80 log_err("LPC: Cannot open IO window: %lx size %lx\n",
81 bridge_base, size - bridged_size);
82 log_err("No more IO windows\n");
86 lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
88 pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir,
91 log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n",
92 lgir_reg_num, bridge_base, window_size);
94 bridged_size += window_size;
95 bridge_base += window_size;
101 void lpc_io_setup_comm_a_b(void)
103 /* ComA Range 3F8h-3FFh [2:0] */
104 u16 com_ranges = LPC_IOD_COMA_RANGE;
105 u16 com_enable = LPC_IOE_COMA_EN;
107 /* Setup I/O Decode Range Register for LPC */
108 pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
109 /* Enable ComA and ComB Port */
110 lpc_enable_fixed_io_ranges(com_enable);
113 static const struct udevice_id apl_lpc_ids[] = {
114 { .compatible = "intel,apl-lpc" },
118 /* All pads are LPC already configured by the hostbridge, so no probing here */
119 U_BOOT_DRIVER(apl_lpc_drv) = {
120 .name = "intel_apl_lpc",
122 .of_match = apl_lpc_ids,