1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
15 #include <acpi/acpi_s3.h>
16 #include <asm/intel_pinctrl.h>
18 #include <asm/intel_regs.h>
20 #include <asm/msr-index.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/systemagent.h>
24 #include <asm/arch/fsp/fsp_configs.h>
25 #include <asm/arch/fsp/fsp_s_upd.h>
26 #include <linux/bitops.h>
27 #include <asm/arch/fsp_bindings.h>
29 #define PCH_P2SB_E0 0xe0
30 #define HIDE_BIT BIT(0)
32 int fsps_update_config(struct udevice *dev, ulong rom_offset,
35 struct fsp_s_config *cfg = &upd->config;
38 if (IS_ENABLED(CONFIG_HAVE_VBT)) {
39 struct binman_entry vbt;
43 ret = binman_entry_find("intel-vbt", &vbt);
45 return log_msg_ret("Cannot find VBT", ret);
46 vbt.image_pos += rom_offset;
47 vbt_buf = malloc(vbt.size);
49 return log_msg_ret("Alloc VBT", -ENOMEM);
52 * Load VBT before devicetree-specific config. This only
53 * supports memory-mapped SPI at present.
55 bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
56 memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
57 bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
58 if (*(u32 *)vbt_buf != VBT_SIGNATURE)
59 return log_msg_ret("VBT signature", -EINVAL);
61 cfg->graphics_config_ptr = (ulong)vbt_buf;
64 node = dev_read_subnode(dev, "fsp-s");
65 if (!ofnode_valid(node))
66 return log_msg_ret("fsp-s settings", -ENOENT);
68 return fsp_s_update_config_from_dtb(node, cfg);
71 static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
73 pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
74 hide ? HIDE_BIT : 0, PCI_SIZE_8);
77 /* Configure package power limits */
78 static int set_power_limits(struct udevice *dev)
80 msr_t rapl_msr_reg, limit;
82 u32 tdp, min_power, max_power;
88 rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
89 power_unit = 1 << (rapl_msr_reg.lo & 0xf);
91 /* Get power defaults for this SKU */
92 rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
93 tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
94 pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
95 min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
96 max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
98 if (min_power > 0 && tdp < min_power)
101 if (max_power > 0 && tdp > max_power)
104 ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
105 ARRAY_SIZE(override_tdp));
107 return log_msg_ret("tdp-pl-override-mw", ret);
109 /* Set PL1 override value */
111 tdp = override_tdp[0] * power_unit / 1000;
113 /* Set PL2 override value */
115 pl2_val = override_tdp[1] * power_unit / 1000;
117 /* Set long term power limit to TDP */
118 limit.lo = tdp & PKG_POWER_LIMIT_MASK;
119 /* Set PL1 Pkg Power clamp bit */
120 limit.lo |= PKG_POWER_LIMIT_CLAMP;
122 limit.lo |= PKG_POWER_LIMIT_EN;
123 limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
124 PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
126 /* Set short term power limit PL2 */
127 limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
128 limit.hi |= PKG_POWER_LIMIT_EN;
130 /* Program package power limits in RAPL MSR */
131 msr_write(MSR_PKG_POWER_LIMIT, limit);
132 log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
133 100 * (tdp % power_unit) / power_unit);
134 log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
135 100 * (pl2_val % power_unit) / power_unit);
138 * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
139 * instead of MMIO, so disable LIMIT_EN bit for MMIO
141 writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
142 writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
147 int p2sb_unhide(void)
149 pci_dev_t dev = PCI_BDF(0, 0xd, 0);
152 p2sb_set_hide_bit(dev, 0);
154 pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
156 if (val != PCI_VENDOR_ID_INTEL)
157 return log_msg_ret("p2sb unhide", -EIO);
162 /* Overwrites the SCI IRQ if another IRQ number is given by device tree */
163 static void set_sci_irq(void)
165 /* Skip this for now */
168 int arch_fsps_preinit(void)
170 struct udevice *itss;
173 ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
175 return log_msg_ret("no itss", ret);
177 * Snapshot the current GPIO IRQ polarities. FSP is setting a default
178 * policy that doesn't honour boards' requirements
180 irq_snapshot_polarities(itss);
183 * Clear the GPI interrupt status and enable registers. These
184 * registers do not get reset to default state when booting from S5.
186 ret = pinctrl_gpi_clear_int_cfg();
188 return log_msg_ret("gpi_clear", ret);
193 int arch_fsp_init_r(void)
195 #ifdef CONFIG_HAVE_ACPI_RESUME
196 bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
200 struct udevice *dev, *itss;
206 * This must be called before any devices are probed. Put any probing
207 * into arch_fsps_preinit() above.
209 * We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
210 * force PCI to be probed.
212 ret = fsp_silicon_init(s3wake, false);
216 ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
218 return log_msg_ret("no itss", ret);
219 /* Restore GPIO IRQ polarities back to previous settings */
220 irq_restore_polarities(itss);
225 return log_msg_ret("unhide p2sb", ret);
227 /* Set RAPL MSR for Package power limits*/
228 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
230 return log_msg_ret("Cannot get northbridge", ret);
231 set_power_limits(dev);
234 * FSP-S routes SCI to IRQ 9. With the help of this function you can
235 * select another IRQ for SCI.