1 /* SPARC Processor specifics
2 * taken from the SPARC port of Linux (ptrace.h).
5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __ASM_SPARC_PROCESSOR_H
11 #define __ASM_SPARC_PROCESSOR_H
13 #include <asm/arch/asi.h>
17 /* All LEON processors supported */
21 /* other processors */
22 #error Unknown SPARC Processor
27 /* flush data cache */
28 static __inline__ void sparc_dcache_flush_all(void)
30 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
33 /* flush instruction cache */
34 static __inline__ void sparc_icache_flush_all(void)
36 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory");
39 /* do a cache miss load */
40 static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned
43 unsigned long long retval;
44 __asm__ __volatile__("ldda [%1] %2, %0\n\t":
45 "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
49 static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr)
52 __asm__ __volatile__("lda [%1] %2, %0\n\t":
53 "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
57 static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long
60 unsigned short retval;
61 __asm__ __volatile__("lduha [%1] %2, %0\n\t":
62 "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
66 static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long
70 __asm__ __volatile__("lduba [%1] %2, %0\n\t":
71 "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
75 /* do a physical address bypass write, i.e. for 0x80000000 */
76 static __inline__ void sparc_store_reg_bypass(unsigned long paddr,
79 __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr),
80 "i"(ASI_BYPASS):"memory");
83 static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr)
86 __asm__ __volatile__("lda [%1] %2, %0\n\t":
87 "=r"(retval):"r"(paddr), "i"(ASI_BYPASS));
91 /* Macros for bypassing cache when reading */
92 #define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address))
93 #define SPARC_NOCACHE_READ(address) sparc_load_reg_cachemiss((unsigned int)(address))
94 #define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address))
95 #define SPARC_NOCACHE_READ_BYTE(address) sparc_load_reg_cachemiss_byte((unsigned int)(address))
97 #define SPARC_BYPASS_READ(address) sparc_load_reg_bypass((unsigned int)(address))
98 #define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value))
102 #endif /* __ASM_SPARC_PROCESSOR_H */